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Rev. 1.0
3. Memory Regions
The following table lists some key terms for writing firmware for the Si4010:
Term
Definition
8051 Internal
Memory
256 bytes of RAM internal to the 8051 MCU. Fastest for MCU to access. It is broken into
three categories, DATA, IDATA and SFR space. See below for a description of these.
DATA
Portion of the internal memory at addresses 0x00 through 0x7F. This memory can be
accessed both directly and indirectly.
DATA is a recognized Keil compiler keyword.
IDATA
Portion of the internal memory occupying addresses 0x80 through 0xFF. This memory can
only be accessed indirectly. IDATA is a recognized Keil compiler keyword.
SFR Space
Special Function Register Space is located in internal memory at addresses 0x80 through
0xFF. This memory can only be accessed directly.
CODE
XDATA
This is both user code memory (CODE) and external data memory (XDATA). Residing at
addresses 0x0000 through 0x11FF. In the Si4010 this space is equivalent to the 4.5 kB of
on chip RAM. CODE/XDATA RAM is where the user application is run from.
CODE and XDATA are recognized Keil compiler keywords.
XREG
Refers to the set of hardware registers located in XDATA address space at addresses
0x4000 through 0x40FF. More information on XREGs can be found in the Si4010 data
sheet.
This is not a recognized Keil compiler keyword.
ROM
Read only memory containing all the API functions. Residing at CODE addresses 0x8000
through 0xAFFF. The CPU executes ROM code directly. ROM is not readable by the user
application.
NVM
Non-Volatile Memory. Each bit can only be written as 1 once (One Time Programmable,
OTP). Code stored in this memory is intended to be loaded into RAM upon boot. It is also
possible for the application to copy code from NVM using the NVM Copy Module. Virtually
mapped to addresses 0xE000 through 0xFFFF. Only accessible by using API functions.
Only formatted data programmed by the NVM composer/programmer are available to be
loaded at boot time or at runtime by bNvm_CopyBlock() function. There is not byte by byte
direct access to NVM.
MTP
128 bits of Multi-Time Programmable Memory (EEPROM). This memory is mapped as read
only at XDATA addresses 0x4040 to 0x404F. Writing to MTP can only be done through the
MTP API Module. User should use the MTP API for read access as well.
HVRAM
HVRAM in the Si4010 consists of 64 bits (8 bytes) of battery backed RAM. As long as the
power is connected to the chip, the HVRAM keeps its content. The content of the HVRAM
is not affected by shutting down the chip by vSys_Shutdown() function. Only accessible by
using the HVRAM API module functions.