AN370
Rev. 1.0
5
3.1. 8051 Internal Memory
Figure 1 shows the Si4010 memory which is internal to the 8051 MCU.
Figure 1. CPU Internal Memory Organization
3.2. Memory Map
After the chip boots, the memory on the Si4010 is mapped as shown in Figure 2. The 4.5 kB RAM section is
accessible both as CODE and XDATA (MOVC and MOVX instructions). The XREG region is accessible only as
XDATA (MOVX). The ROM is not accessible as data, but the code residing in ROM can be executed. The NVM is
virtually mapped into this region, but is not directly accessible by CPU. The NVM API functions must be used to
access the NVM.
Figure 2. Si4010 Unified CODE/XDATA Memory Organization
Indirect addressing only
by @Ri pointers
DATA
IDATA
SFR
(DATA)
0x00
0x7F
0x80
0xFF
0x80
0xFF
MOV A, @Ri
Direct addressing only
MOV A, addr
Both direct and indirect addressing
Internal Memory
0x0000
RAM 4.5K
0xFFFF
CODE/
XDATA
0x8000
0x4000
64
KB
16KB
ROM 12K
XREG
0xE000
NVM 8K
0x11FF
0x40FF
0xAFFF
Virtual mapping, not directly
accessible by CPU