Interface Details
9
SPRUIE6 – April 2017
Copyright © 2017, Texas Instruments Incorporated
AMIC110 Industrial Communications Engine (AMIC110 ICE)
2.4.2
Industrial Ethernet Resistor Strapping
The DP83822 PHY uses a four-level configuration based on resistor strappings, which generate four
distinct voltages ranges. These resistors are connected to the RX data and control pins that are normally
driven by the PHY and are inputs to the AMIC. The voltage ranges follow:
•
Mode 1 – 0 V to 0.3234 V
•
Mode 2 – 0.4884 V to 0.5973 V
•
Mode 3 – 0.7491 V to 0.9141 V
•
Mode 4 – 2.2902 V to 3.3 V
Mid-level voltages can result in high leakage currents and are detrimental to the long-term reliability of the
AMIC 110 I/O cells connected to the strapping resistor. To avoid this situation, only pullup and pulldown
resistors are used to pull the I/O cells as close as possible to 0 V or 3.3 V; this limits the selection of
configurations to those that can be selected by using Mode 1 or Mode 4. The DP83822 device and the
AMIC110 include internal pulling resistors. The values of the external pull resistors are selected to provide
a voltage at the pins of the AMIC110 as close to ground or 3.3 V as possible.
2.4.3
Software Steps for Industrial Ethernet Resistor Strapping
The following steps should be performed before the AMIC110 pins are configured to operate in their
intended application.
Software should maintain the power on default state for LCD_DATA[15:0] pins (except LCD_DATA6 and
LCD_DATA7). LCD_DATA6 and LCD_DATA7 should have their internal pulldown resistors turned on; this
holds the LCD_DATA6 and LCD_DATA7 pins in a valid logic state once the SYSBOOT buffers are turned
off.
The GPMC_AD9 and LCD_PCLK pins should be in their power-on default configuration operating in their
respective GPIO mode with internal pullown resistors turned on. Software should turn off the internal pull
resistors on these pins; this prevents AMIC110 internal pull resistors from interfering with the
bootstrapping of Ethernet PHY1.
The power on default state of the GPMC_A[11:0] and LCD_AC_BIAS_EN pins are configured to their
respective GPIO mode with internal pulldown resistors turned on. The power-on default state of the
GPMC_WPn and GPMC_WAIT0 pins are configured to their respective GPIO mode with internal pull-up
resistors turned on. Software should turn off internal pull resistors on all of these pins to prevent AMIC110
internal pull resistors from interfering with the bootstrapping of Ethernet PHY2 (U5).
Next, software should configure GPIO2_19 to be an output that is driven high to turn off the SYSBOOT
buffers. After a 100-µs delay, the GPMC_AD13 pin should be configured to operate as GPIO1_13 with its
output enabled and driven high; this releases the reset to both Ethernet PHYs, allowing them to latch their
bootstrap inputs.
After another delay of 100 µs, isolation switch U10 must be turned on by enabling the output of GPIO2_18
and driving it high.
The next step is to configure all AMIC110 pins to their intended application and execute the application
code.
