UBX-G7020 - Hardware Integration Manual
Design-in
GPS.G7-HW-10003
Objective Specification
Page 19 of 74
2.2.3
Communication interfaces
A UART, SPI and DDC (I
2
C compatible) interface is available to communicate with a host on the UBX-G7020.
There is also a USB interface available on dedicated pins, see section 2.7.
The UART, SPI and DDC pins are supplied by and operate at VDD_IO voltage levels.
There are 4 pins (PIO6 to PIO9) to provide a UART, DDC and SPI interface for communication with a host CPU.
These 4 PIOs can be configured as either 1 x UART and 1 x DDC or a single SPI interface selectable by the PIO10
(D-SEL pin). Table 5 below provides the port mapping details.
If the SPI port is used for communication to a host CPU, there is the possibility to configure the UBX-G7020 so
that the UART is mapped to PIO15 and PIO16. Thus the UART can be used as a debug interface or a second
communication interface if needed. To remap the UART use the Low Level Configuration, see section 2.10.2 and
u-blox 7 Receiver Description including Protocol Specification
PIO #
PIO10 (D_SEL) = “high”
(left open)
PIO10 (D_SEL) = “Low”
(connected to GND)
PIO10 (D_SEL) = “Low”
(connected to GND) and
UART remapped
PIO6
UART TX
SPI MISO
SPI MISO
PIO7
UART RX
SPI MOSI
SPI MOSI
PIO8
DDC SCL
SPI CLK
SPI CLK
PIO9
DDC SDA
SPI CS
SPI CS
PIO15
ANT_OK
ANT_OK
UART TX
PIO16
ANT_OFF
ANT_OFF
UART RX
Table 5: Communication Interfaces overview
It is not possible to have both the DDC and SPI interfaces active simultaneously for communication with
a host.
For debugging purposes it is recommended to have a second interface independent from the
application available via test-points.
The optional remapped UART interface is not available in Safe Boot Mode, see section 2.2.6.
For each interface, a dedicated pin can be defined to indicate that data is ready to be transmitted. This Tx-ready
pin can be mapped to any unused PIO pin. Each Tx-ready pin is associated with a particular interface and cannot
be shared. If the nominated PIO has another function by default, it needs to be disabled before configuring the
Tx-ready signal to that PIO pin. For configuration of the Tx-ready feature see
u-blox 7 Receiver Description
including Protocol Specification
2.2.3.1
UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports configurable
data rates of which the default is 9600 baud. The signals levels are related to VDD_IO supply voltage. An
interface based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs such as the Maxim
MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see
u-blox 7
Receiver Description including Protocol Specification
[3].).
The UART can be permanently remapped by Low Level Configuration to PIO15 and PIO16, see section
2.10.2.
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