UBX-G7020 - Hardware Integration Manual
Design-in
GPS.G7-HW-10003
Objective Specification
Page 44 of 74
Topic
Setting
Description
Default Setting
Remarks
UART
UART Baud Rate
Configures the Baud Rate
9600 baud
UART Remapping
In case SPI is used for communication to host, UART can be
remapped to PIO15 and PIO16 if needed
Not remapped
Remapped UART
cannot be used in
Safe Boot Mode!
SQI
Flash
VDD_IO POR
Sets the threshold for the VDD_IO POR. The VDD_IO POR
threshold needs to be set according to supply voltage range of
external SQI Flash (1.8V / 3V).
1.8V
Must be always
configured
in
eFuse!
Power
DCDC converter
Enables the optional DCDC converter
Disabled
Main
Clock
Single Crystal
RTC is derived from Main Clock (no RTC crystal needed)
Disabled
Clock type
What kind of clock source is used; TCXO or Crystal
Crystal
Clock data
Additional information to the clock source; load of crystal or
supply of TCXO
19pF load
Active
Antenna
/ LNA
Antenna
supervisor/ external
LNA enable pin
There are 2 different antenna supervisors available, a 2-pin and
a 3-pin version. Additionally on enable signal can be made
available to turn off external LNA in Power Save Mode.
2-pin
Antenna
Supervisor
ANT_OFF
and
ANT_OK
Polarity of Antenna
supervisor / LNA
enable pin
Polarity of the antenna supervisor pins/ LNA enable pin can be
configured.
USB
USB
powered
mode
Self or bus powered device
Self powered
USB vendor ID
Sets the vendor ID
0x1546
USB vendor string
Sets the vendor string
u-blox AG - www.u-blox.com
USB product ID
Sets the product ID
0x01A7
USB product string
Sets the product string
u-blox 7 - GPS/GNSS Receiver
Table 12: Low Level Configuration overview and default settings
For detailed information about how to set the Low Level Configuration in SQI flash or eFuse see
u-blox 7
Receiver description including protocol specification
The VDD_IO threshold (POR_IO) which has to match the supply voltage of the SQI flash, must be always
configured in eFuse; must not be set in SQI Flash!
The current Low Level Configuration can be checked by polling the UBX-MON-LLC message, see
u-blox 7
Receiver description including protocol specification
2.10.2.1
One Time Programmable eFuse
The UBX-G7020 eFuse is implemented as an OTP memory which can hold all the Low Level Configuration
settings. The eFuse is supplied by VDD_IO and consumes ~10mA during writing.
The eFuse can be accessed and changed by any communication port. To write a Low Level Configuration into
the eFuse, the UBX-CFG-OTP message has to be used. For detailed information see
u-blox 7 Receiver description
including protocol specification
In Safe Boot Mode (e.g. in production for designs with external SQI flash) the eFuse cannot be accessed by USB,
because of the unknown main clock source, see section 2.2.6. Access via UART is possible after sending a
training sequence to the UBX-G7020. With a remapped UART it is not possible to communicate to the UBX-
G7020 in Safe Boot Mode. A DDC and SPI communication method is the most convenient mode to set the eFuse
Low Level Configuration correctly as the clock is provided by the host.
VDD_IO monitor level (POR_IO) level must always be set in eFuse!
2.10.2.2
Low Level Configuration by Configuration Pins (for designs without external SQI Flash)
If no external SQI Flash is connected, PIO0 to PIO5 can be used for some low level configuration settings. If PIO5
(CONFIG_SEL), is connected to GND it enables the Low Level Configuration pins PIO0 to PIO4. The part of the
Low Level Configuration set by the configuration pins has a higher priority than the Low Level Configuration
held in the eFuse. For information about the Low Level Configuration pins see section 2.2.2.
