43
I/O Port Map
3
Any function on a multifunction device can be connected to any of the INTx# lines.
The Interrupt Pin register defines which INTx# line the function uses to request an
interrupt. If a device implements a single INTx# line, it is called INTA#; if it
implements two lines, they are called INTA# and INTB#; and so forth. For a
multifunction device, all functions may use the same INTx# line or each may have its
own (up to a maximum of four functions) or any combination thereof. A single
function can never generate an interrupt request on more than one INTx# line.
The slave PIC accepts the CompactPCI interrupts through lines that are defined by
the BIOS. The BIOS defines which interrupt line to utilize depending on which system
requires the use of the line.
The PCI-to-PCI Bridge has the capability of generating a Non-Maskable Interrupt
(NMI) via the PCI SERR# line. Table 3-4 describes the register bits that are used by the
NMI. The SERR interrupt is routed through logic back to the NMI input line on the
CPU. The CPU reads the NMI Status Control register to determine the NMI source
(bits set to 1). After the NMI interrupt routine processes the interrupt, software clears
the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI
Enable and Real-Time Clock register can mask the NMI signal and disable/enable all
NMI sources.
Table 3-4 NMI Register Bit Descriptions
Status Control Register
(I/O Address $061, Read/Write, Read Only)
Bit 7
SERR# NMI Source Status (Read Only) - This bit is set to 1 if a system board agent detects
a system board error. It then asserts the PCI SERR# line. To reset the interrupt, set bit 2 to
0 and then set it to 1. When writing to port $061, bit 7 must be 0.
Bit 2
PCI SERR# Enable (Read/Write) - 1 = Clear and Disable, 0 = Enable
Enable and Real-Time Clock Address Register
(I/O Address $070, Write Only)
Bit 7
NMI Enable - 1 = Disable, 0 = Enable
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