60 PPC11A 6U VME Single Board Computer
Publication No. PPC11A-HRM/1
4.21
Timers
The processor contains one 32-bit decrementer timer per thread, i.e. eight for the
T2081 and four for the T1042. The processor also contains one 64-bit timebase
counter/timer per physical core, i.e. 4 for both processor types.
The processor contains eight 31-bit global timers within the Multicore Programmable
Interrupt Controller (MPIC) block. Up to four MPIC global timers may be cascaded
to form larger timers.
T
he operating system may use some of these timers,
making them un
available to the
user.
The FPGA provides four general purpose 32-bit timers. See the
more details
.
4.21.1 Watchdog Timer
The FPGA provides a Watchdog timer. This can generate interrupts to the processor
and reset the PPC11A on expiry.
The Watchdog is a 32-bit count-down timer, the period of which is programmable.
The counter is clocked by the local bus clock, giving a resolution of 20 ns and a
maximum timeout period of 85.9 seconds (assuming a 50 MHz bus speed).
Following reset, the Watchdog timer is initially disabled. It can be enabled by
writing a “01” followed by “10” pattern to the relevant control register. When
enabled, the counter is reloaded to the preset value, and the reset and interrupt bits
are cleared (if the preset counter value is higher than the interrupt value).
Once enabled, the Watchdog must be serviced periodically. If the counter reaches
zero before the Watchdog is serviced, then a hard reset is generated. The Watchdog
can be serviced by writing a “01” followed by “10” pattern to the relevant control
register. This operation clears the interrupt and reset flags, if set, and reloads the
counter to the preset value.
A programmable interrupt threshold can be set. If the counter reaches this threshold,
then an interrupt is generated to the interrupt controller, which may be routed to the
processor if required.
The Watchdog can be disabled by writing a “01” followed by “10” pattern to the
relevant control register. The status of the Watchdog can also be read from this
register.
See
for more details
.
