Model 8310-XX-X-XN
IM-493
Aeroflex / Weinschel
24
5-3 Status Reporting
The 6853 implements the 488.2 Status Reporting Structure, which utilizes the IEEE488.1 status byte with
additional data structures and rules. The Status Byte Register can be read with either a serial poll (IEEE-488
operation only) or the *STB? Common query command. The Service Request Enable Register (SRE) allows the user
to select which bits in the Status Byte Register may cause service requests. A bit value of one indicates that the
corresponding event is enabled, while a bit value of zero disables an event. The Service Request Enable Register
may be accessed with the *SRE and *SRE? Common commands. The Status Byte Register may be cleared with the
*CLS common command, with the exception of the MAV bit, which is controlled by the operation of the Output Queue.
The SRE Register is set to 0 at power-on, disabling all events.
Status Byte Register/ Service Request Enable Register Formats
D7 D6 D5 D4 D3 D2 D1 D0
RQS ESB MAV
EEQ
Bit Mnemonic
Description
6
RQS
Request Service: This bit, if set, indicates that the device is asserting the SRQ signal.
5
ESB
Event Status Bit: This bit is true when an enabled event in the Event Status Register is
true.
4
MAV
Message Available: This bit is true when there is valid data available in the output queue.
2
EEQ
Error/Event Queue: This bit is true when there is Error/Event data available in the
Error/Event queue.
The Standard Event Status Register is used to report various IEEE 488.2-defined events. The register
contents may be accessed with the *ESR? Command. An Event Status Enable Register allows the user to select
which bits in the ESR that will be reflected in the ESB summary message bit of the Status Byte Register. The Event
Status Enable Register may be accessed with the *ESE and *ESE? Common commands. The Event Status Register
is cleared by an *ESR? Query or *CLS common command. The ESE Register is set to 0 at power-on, disabling all
events.
Standard Event Status Register/ Standard Event Status Enable Register Formats
D7 D6 D5 D4 D3 D2 D1 D0
ON URQ CME EXE DDE QYE RQC OPC
Bit Mnemonic
Description
7
PON
Power On: This bit indicates that the device has powered-on
6
URQ
User Request: This event bit indicates that a local control is causing a
User Request
5
CME
Command Error: The parser has detected a syntax error in the current command.
4
EXE
Execution Error: The command could not be properly executed due to
an illegal input range or other inconsistent data.
3
DDE
Device Dependent Error: A command could not properly complete due to some
device specific error
2
QYE
Query Error: This bit indicates that either an attempt has been made to read data
when there was none present, or that data in the Output Queue has been lost
1
RQC
Request Control: The device is requesting control (not implemented)
0
OPC
Operation Complete: This bit is generated in response to an *OPC command. It
indicates that the ITS 2000 has completed all pending operations.
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