Programmers Model
3-12
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3.6
Exceptions
This section describes the exception model of the processor.
3.6.1
Exception handling
The processor implements advanced exception and interrupt handling, as described in
the
ARMv6-M ARM
.
To minimize interrupt latency, the processor abandons any load-multiple or
store-multiple instruction to take any pending interrupt. On return from the interrupt
handler, the processor restarts the load-multiple or store-multiple instruction from the
beginning.
Note
A processor that implements the 32-cycle multiplier abandons multiplies in the same
way.
This means that software must not use load-multiple or store-multiple instructions when
a device is accessed or memory region that is read-sensitive or sensitive to repeated
writes. The software must not use these instructions in any case where repeated reads
or writes might cause inconsistent results or unwanted side-effects.
The processor implementation can ensure that a fixed number of cycles are required for
the NVIC to detect an interrupt signal and the processor fetch the first instruction of the
associated interrupt handler. If this is done, the highest priority interrupt is jitter-free.
See the documentation supplied by the processor implementer for more information.
To reduce interrupt latency and jitter, the Cortex-M0 processor implements both
interrupt late-arrival and interrupt tail-chaining mechanisms, as defined by the
ARMv6-M architecture.
The processor exception model has the following implementation-defined behavior in
addition to the architecture specified behavior:
•
exceptions on stacking from HardFault to NMI lockup at NMI priority
•
exceptions on unstacking from NMI to HardFault lockup at HardFault priority.
