140
FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
A/D depicts Address and Data bus independent of interface protocol.
Full size transfer is illustrated in the figure below.
Figure 10-1. Full-sized DMA Transfers
1. AP configures PP_SOCK_STAT[N] becomes active when data or space is available.
2. AP configures PP_SOCK_MASK and PP_INTR_MASK register to enable interrupt when socket
is ready with data or empty-buffer for data transfer.
3. Application processor detects this interrupt signaling and reads registers PP_EVENT and
PP_SOCK_STAT_x to know which socket to work on.
4. AP activates socket by writing socket-number, direction and DMA_ENABLE=1 to
PP_DMA_XFER. This causes DMA_ENABLE to assert
1
in a few cycles. AP uses
LONG_TRANSFER=0 for short (single buffer) transfer.
5. Optional register reads are performed from PP_DMA_XFER until PP_DMA_XFER.SIZE_VALID
asserts, after which PP_DMA_SIZE is read to determine buffer/data size. Multiple reads may be
required before the SIZE_VALID asserts.
6. PP_EVENT.DMA_READY asserts after socket has been activated to indicate data transfer can
start. This can occur before, during or after the DMA_SIZE read mentioned above.
7. DMA_SIZE bytes are transferred in an integral number of full bursts. The number of bursts is
rounded up and data beyond the size of buffer for ingress is ignored; reads beyond the size of
data for egress return 0.
8. PP_EVENT.DMA_WMARK de-asserts shortly after the watermark has passed (see burst section
above). Due to pipelining of the interface it may take a couple of cycles before this signal physi-
cally de-assert in the GPIF state machine.
SOCK_STAT[N], DMA_READY and DMA_ENABLE all become zero a few cycles after the last word
of the last burst has been transferred.
If data words are written when DMA_READY=0 (i.e. beyond the end of the buffer or after an error
condition occurred), data will be ignored. Reads under these circumstances will return 0. These
reads or writes themselves represent an error condition if one is not already flagged. Upon (any)
error DMA_ERROR becomes active and DMA_READY de-asserts.
The following diagrams illustrate the sequence of events at the P-Port for read and write transfers:
1.
Asserting a status bit implies setting status bit to 1; and de-asserting a status bit implies setting the
status-bit to 0.
Summary of Contents for EX-USB FX3
Page 8: ...8 FX3 Programmers Manual Doc 001 64707 Rev C Contents...
Page 12: ...12 FX3 Programmers Manual Doc 001 64707 Rev C Introduction...
Page 48: ...48 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Overview...
Page 74: ...74 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Firmware...
Page 76: ...76 FX3 Programmers Manual Doc 001 64707 Rev C FX3 APIs...
Page 84: ...84 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Application Examples...
Page 98: ...98 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Application Structure...
Page 148: ...148 FX3 Programmers Manual Doc 001 64707 Rev C FX3 P Port Register Access...
Page 165: ...FX3 Programmers Manual Doc 001 64707 Rev C 165 FX3 Development Tools Click next...
Page 178: ...178 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools Click on Apply...
Page 180: ...180 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools d Start the GDB server...
Page 185: ...FX3 Programmers Manual Doc 001 64707 Rev C 185 FX3 Development Tools...
Page 186: ...186 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools...
Page 187: ...FX3 Programmers Manual Doc 001 64707 Rev C 187 FX3 Development Tools...
Page 188: ...188 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools...
Page 192: ...192 FX3 Programmers Manual Doc 001 64707 Rev C GPIF II Designer...
