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M68HC08RG/AD

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M68HC08 Family Reference Guide

MOTOROLA

Addressing Modes

Inherent (INH)

The inherent addressing mode has no operand because the opcode contains 
all information necessary to carry out the instruction. Most inherent instructions 
are one byte long.

Immediate (IMM)

The operand in immediate mode instructions is contained in the byte(s) 
immediately following the opcode. The immediate value is one or two bytes, 
depending on the size of the register involved in the instruction.

Direct (DIR)

Most direct mode instructions can access any of the first 256 memory 
addresses with two bytes. The first byte is the opcode, and the second byte is 
the low byte of the operand address. The high byte of the address is assumed 
to be $00.

Extended (EXT)

Extended mode instructions are three bytes in length and can access any 
address in a 64-Kbyte memory map. The first byte is the opcode. The following 
two bytes are the operand addresses.

Indexed (IX, IX1, 
and IX2)

Indexed mode instructions access data with variable addresses. The effective 
address (EA) of the operand is determined by the contents of the register (H:X) 
added to a zero, 8-bit, or 16-bit offset. For one-byte, zero-offset mode 
instructions (IX), X (index register low) contains the low byte of the EA of the 
operand. The value of H (index register high) is $00 if none of the HC08 
instructions that modify H are used, assuring source code compatibility with 
HC05 Family instructions. The sum of H:X is the EA of the operand. For two-
byte, 8-bit offset mode instructions (IX1) the unsigned bytes in H:X added to the 
unsigned byte following the opcode constitutes the EA of the operand. For 
three byte, 16-bit offset mode instructions (IX2), the unsigned bytes in H:X 
added to the 16-bit unsigned word following the opcode constitute the EA of the 
operand.

Stack Pointer 
(SP1 and SP2)

Stack pointer (SP) mode instructions operate like indexed instructions, except 
that the offset is added to the 16-bit SP. Stack pointer, 8-bit offset instructions 
(SP1) are three-byte instructions. The EA of the operand is formed by adding 
the unsigned byte in the SP register to the unsigned byte following the opcode. 
Stack pointer, 16-bit offset instructions (SP2) are four-byte instructions. The EA 
of the operand is formed by adding the unsigned bytes in the 16-bit SP register 
to the 16-bit unsigned word following the opcode.

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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Summary of Contents for M68HC08AD

Page 1: ...X 1 5 0 STACK POINTER SP 1 5 0 PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER CCR V 1 1 H I N Z C CARRY BORROW FLAG C TWO S COMPLEMENT OVERFLOW FLAG V ZERO FLAG Z HALF CARRY FLAG H NEGATIVE FLAG N IN...

Page 2: ...e it is the user s responsibility to save and restore it prior to returning IRQINT PSHH Interrupt service routine PULH RTI Figure 3 H Register Storage CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTE...

Page 3: ...ith read gets Boolean AND Boolean OR Boolean exclusive OR Multiply Divide Concatenate Add Negate two s complement Sign extend CPU Registers A Accumulator CCR Condition code register H Index register h...

Page 4: ...it 0 carry out of bit 7 Bit Status BEFORE Execution of an Instruction n 7 6 5 0 1 1 For 2 byte operations such as LDHX STHX and CPHX n 15 refers to bit 15 of the 2 byte word or bit 7 of the most signi...

Page 5: ...o a 16 bit value The instruction treats this value as an address in the 64 Kbyte address space oprx8 Any label or expression that evaluates to an unsigned 8 bit value used for indexed addressing oprx1...

Page 6: ...inter SP SP M M is sign extended to a 16 bit value IMM A7 ii 2 AIX opr8i Add Immediate Value Signed to Index Register H X H X H X M M is sign extended to a 16 bit value IMM AF ii 2 AND opr8i AND opr8a...

Page 7: ...ch if IRQ pin 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin 0 REL 2E rr 3 BIT opr8i BIT opr8a BIT opr16a BIT oprx16 X BIT oprx8 X BIT X BIT oprx16 SP BIT oprx8 SP Bit Test A M CCR Upda...

Page 8: ...rr 5 5 5 5 5 5 5 5 BSET n opr8a Set Bit n in Memory Mn 1 DIR b0 DIR b1 DIR b2 DIR b3 DIR b4 DIR b5 DIR b6 DIR b7 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BSR rel Branch to Subr...

Page 9: ...CPX opr16a CPX oprx16 X CPX oprx8 X CPX X CPX oprx16 SP CPX oprx8 SP Compare X Index Register Low with Memory X M CCR Updated But Operands Not Changed IMM DIR EXT IX2 IX1 IX SP2 SP1 A3 B3 C3 D3 E3 F3...

Page 10: ...ee ff ff 4 5 6 5 4 LDA opr8i LDA opr8a LDA opr16a LDA oprx16 X LDA oprx8 X LDA X LDA oprx16 SP LDA oprx8 SP Load Accumulator from Memory A M 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 A6 B6 C6 D6 E6 F6 9ED6 9EE...

Page 11: ...prx16 SP ORA oprx8 SP InclusiveOR Accumulator and Memory A A M 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 AA BA CA DA EA FA 9EDA 9EEA ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 2 5 4 PSHA Push Accumulator onto Sta...

Page 12: ...1 1 INH 99 1 SEI Set Interrupt Mask Bit I 1 1 INH 9B 2 STA opr8a STA opr16a STA oprx16 X STA oprx8 X STA X STA oprx16 SP STA oprx8 SP Store Accumulator in Memory M A 0 DIR EXT IX2 IX1 IX SP2 SP1 B7 C7...

Page 13: ...to X Index Register Low X A INH 97 1 TPA Transfer CCR to Accumulator A CCR INH 85 1 TST opr8a TSTA TSTX TST oprx8 X TST X TST oprx8 SP Test for Negative or Zero M 00 A 00 X 00 M 00 M 00 M 00 0 DIR IN...

Page 14: ...or 16 bit offset For one byte zero offset mode instructions IX X index register low contains the low byte of the EA of the operand The value of H index register high is 00 if none of the HC08 instruct...

Page 15: ...y indexed to direct with post increment of H X IX D is a two byte addressing mode The operand addressed by H X is stored in the direct page location addressed by the byte following the opcode Memory t...

Page 16: ...SL 2 IX1 5 LSL 3 SP1 3 LSL 1 IX 2 PULX 1 INH 1 CLC 1 INH 2 EOR 2 IMM 3 EOR 2 DIR 4 EOR 3 EXT 4 EOR 3 IX2 5 EOR 4 SP2 3 EOR 2 IX1 4 EOR 3 SP1 2 EOR 1 IX 9 5 BRCLR4 3 DIR 4 BCLR4 2 DIR 3 BHCS 2 REL 4 RO...

Page 17: ...2A 4A J 6A j 0B VT 2B 4B K 6B k 0C FF 2C comma 4C L 6C l 0D CR return 2D dash 4D M 6D m 0E SO 2E period 4E N 6E n 0F SI 2F 4F O 6F o 10 DLE 30 0 50 P 70 p 11 DC1 31 1 51 Q 71 q 12 DC2 32 2 52 R 72 r...

Page 18: ...3 0 4th Hex Digit 3rd Hex Digit 2nd Hex Digit 1st Hex Digit Hex Decimal Hex Decimal Hex Decimal Hex Decimal 0 0 0 0 0 0 0 0 1 4 096 1 256 1 16 1 1 2 8 192 2 512 2 32 2 2 3 12 288 3 768 3 48 3 3 4 16...

Page 19: ...ber you are converting The corresponding hexadecimal digit is the most significant hexadecimal digit of the result Subtract the decimal number found from the original decimal number to get the remaini...

Page 20: ...rent applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does no...

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