MCF5282 User’s Manual Errata, Rev. 15
Errata for Revision 2.3
Freescale Semiconductor
4
Figure 23-18/Page 23-18
Remove the two 16-bit divider blocks from timer input, as the divider is not available using
external clock sources.
Section 23.5.1.2.2/Page
23-19
Remove 16-bit divider from equation, as the divider is not available using external clock
sources.
Section 25.5.8/Page 25-25 Change end of last sentence from “...and can be written by the host to ‘0’.” to “...and can be
written by the host to ‘1’.”
Table 25-17/Page 25-29
Remove the following information from the BITERR and ACKERR descriptions as these
fields are read only: “To clear this bit, first read it as a one, then write it as a one. Writing
zero has no effect.” (This is a rescindment of a previous documentation errata.)
Change last sentence in ERRINT description from: “To clear this bit, first read it as a one,
then write as a zero. Writing a one has no effect.” to “To clear this bit, first read it as a
one, then write a one. Writing a zero has no effect.”
Add the following information to the BOFFINT and WAKEINT descriptions: “To clear this bit,
first read it as a one, then write it as a one. Writing zero has no effect.”
Table 25-17/Page 25-27
Definition of bits ERRINT and BOFFINT are incorrect for register ESTAT: ERRINT should
be bit 1, BOFFINT should be bit 2. They should be cleared by writing a one instead of a
zero.
Table 26-1/Page 26-5
Change description field for DTOUT1 from “DMA timer 1 output / Port TD[3]...” to “DMA
timer 1 output / Port TD[2]...”
Change description field for DTIN0 from “DMA timer 0 input / Port TD[3]...” to “DMA timer 1
output / Port TD[1]...”
Change description field for DTOUT0 from “DMA timer 0 output / Port TD[3]...” to “DMA
timer 1 output / Port TD[0]...”
Table 30-12/Page 30-14
Add the following note to the PBR[Address] field description:
Note: PBR[0] should always be loaded with a 0.
Table 30-20/Page 30-35
Change CSR’s initial state to 0x0000_0000.
Chapter 33
Add the following note:
“It is crucial during power-up that VDD never exceeds VDDH by more that ~0.3V. There
are diode devices between the two voltage domains, and violating this rule can lead to a
latch-up condition.”
Table 33-3/Page 33-3
In the V
OH
and V
OL
entries, change the respective I
OH
and I
OL
specs from “I
OH
= -2.0mA”
to “I
OH
= -5.0mA” and “I
OL
= +2.0mA” to “I
OL
= +5.0mA”
Table 33-8/Page 33-7
In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device were
listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol
f
sys(max)
, as shown below:
Table 1. MCF5282UM Rev 2.3 Errata (continued)
Location
Description
Characteristic
Symbol
Min
Max
Unit
66MHz
80MHz
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode
f
ref_crystal
f
ref_ext
f
ref_1:1
2
2
33.33
8.33
8.33
66.66
10.0
10.0
80
MHz
System Frequency
1
External Clock Mode
On-Chip PLL Frequency
f
sys
0
f
ref
/ 32
f
sys(max)
66.66
66.66
f
sys(max)
80
80
MHz
