MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-1
Preliminary
Chapter 4
Frequency Modulated Phase Locked Loop (FMPLL)
4.1
Introduction
The FMPLL module is a frequency modulated phase-locked loop that has been optimized to generate
voltage controlled oscillator (VCO) frequencies from 192 MHz to 500 MHz based on an input clock range
of 4 MHz to 40 MHz. The frequency multiplication, output dividers, and the frequency modulation
waveform are register-programmable through a peripheral bus interface.
NOTE
Although this PLL is basically the same PLL that is used on other Power PC
parts, its implementation is different, owing to the use of an internal 16 MHz
IRC, low-power modes, and other features specific to the 5510 family.
4.1.1
Block Diagram
A simplified block diagram of the FMPLL illustrates the functionality and interdependence of major
blocks (see
). Shaded blocks represent analog circuit components that make up the core analog
portion of the FMPLL. The complete FMPLL closed-loop system contains the feedback divider (EMFD)
and output divider (ERFD), which are implemented with standard cell core logic elements. Refer to
Section 4.4.3.3, “PLL Normal Mode Without FM
,” for details on each sub-block.
Figure 4-1. FMPLL Block Diagram
FMDAC_STEP[0:9]
D2AFM
CALDAC
EXTAL
EPREDIV
PFD
FILTER
VCO
ERFD
LOC_PLL
LOC_REF
EMFD
PLL Clock
Out
Used to create the
loss of clock reset
request and decide
which PLL mode to
switch to when
these things happen