161
CHAPTER 8 16-BIT RELOAD TIMER
■
Operating States of the Counter
The CNTE bit of the control register and the internal signal WAIT determine the counter status. The states
that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); the startup trigger wait
state, when CNTE=1 and WAIT=1 (WAIT status); and the operation state, when CNTE=1 and WAIT=0
(RUN state). Figure 8.4-5 shows the state transitions.
Figure 8.4-5 Status Transitions of Counter
State transition due to register access
Reset
Reset
STOP
OP
CNTE=0, WAIT=1
Counter: Holds the value
w
hen it
stops
Undefined right after reset
RUN
UN
CNTE=1, WAIT=0
Counter: Running
WAITST
AITST
CNTE=1, WAIT=1
Counter: Holds the value
w
hen it
stops
Undefined right after reset
until data is loaded
LOAD
AD
CNTE=1,WAIT=0
Loads contents of reload register into counter
State transition due to hard
w
are
CNTE=1
TRG=0
CNTE=1
TRG=1
TRG=1
TRG=1
RELD
•
UF
RELD
•
UF
Load completed
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......