Revision B
5-11
CPU Theory of Operation: Theory of Operation
MAC 5000 resting ECG analysis system
2000657-002
transceiver and a 3-way bi-directional multiplexer to attach to the three
BBus microcontrollers. From the programmer’s standpoint, BBus
operates like SPI, where each transaction exchanges a single byte
between the host and peripheral.
UARTS
Two full duplex UARTs are provided for COM3 and COM4. Each has
programmable bit rates, but no handshake lines are provided. The
receiver is double buffered, the transmitter single buffered. To reduce
cost and conserve panel space, the COM3 and COM4 signal lines are
connected to the COM1 handshake lines, so COM1 handshake
functionality must be sacrificed to use COM3 or COM4. The COM3 and
COM4 TxD outputs may be tri-stated to allow the COM1 handshake
output lines to operate normally.
The handshake lines are shared as follows:
■
COM3 TxD
COM1 RTS
■
COM3 RxD
COM1 CTS
■
COM4 TxD
COM1 DTR
■
COM4 RxD
COM1 DSR
The available bit rates are: 1200, 4800, 9600, 19.2K, 38.4K and 115.2Kbps.
The only frame format supported is 8N1.
Interrupts for COM3,4 are shared on a single IRQ vector. Tx buffer ready,
Tx buffer clear and Rx buffer full status bits are provided.
Note that when COM2 is in IrDA mode the COM2 handshake lines are
not used and COM3 and COM4 may be used without loss of COM2
functionality.
PWM Analog Outputs
Four PWM channels are provided for the generation of analog outputs.
Three of the outputs are available on the Analog I/O connector, the
fourth is available internally for future use. One of the PWM channels
provides 12-bit resolution at 6KHz cycle rate, the other three provide 8-
bit resolution at 96KHz cycle rate. The StrongARM simply writes the
desired value into a PWM data register and the output duty cycle
changes on the next PWM cycle. External analog circuitry converts the
PWM logic signals to smooth analog voltages. The 12-bit PWM channel
is intended for ECG output and produces a swing of +10 to -10V. The two
8-bit channels provide a unipolar 10V output. Regardless of the
resolution or swing range of each PWM channel, the FPGA treats the
data value as a signed 16-bit number representing a voltage from +10V
(0x7fff) to -10V(0x8000). Logic in each PWM channel ensures that the
closest possible voltage is generated for each data value (ex. 0x8000 on
an 8-bit channel produces zero volts output).
Beep Generator
A simple tone generator with two volume levels provides the system
beep tones. Frequencies of 250Hz, 500Hz and 1KHz are provided at both
low and high volume. The logic level output signal drives a speaker
through an open collector transistor driver.
Summary of Contents for MAC 5000
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