42 SBC330 3U VPX Single Board Computer
Publication No. SBC330-0HH/3
5.10 Resets, Interrupts and Error Reporting
The
following
table
shows
the
various
external
interrupt
sources
to
the
processor
and
their
relative
priorities.
It
also
shows
whether
the
previous
state
of
the
processor
is
recoverable.
5.10.1 Hard reset
A
hard
reset
(HRESET
signal)
resets
the
MPC8641D
(including
the
processing
cores)
and
all
other
devices
on
the
board
that
require
resetting.
When
released
from
reset,
Processing
Core
0
begins
executing
from
the
Boot
Flash
at
address
0xFFF0
0100.
A
hard
reset
is
initiated
when
one
of
the
following
hardware
events
occur:
• Any
of
the
power
supplies
fall
outside
specification
• The
VPX
backplane
SYSRESET~
signal
is
asserted
• The
processor
HRESET_REQ~
output
is
asserted
• The
HRESET~
signal
on
the
BDM
Header
is
asserted
• The
reset
output
of
the
BMM
is
asserted
• Either
of
the
two
watchdog
timers
expire
• The
front
panel
switch
is
activated
(build
levels
1
to
3
only)
• The
duration
of
the
internal
hard
reset
signal
is
at
least
10ms
The
processing
cores
may
be
individually
reset
by
software
using
the
Processor
Core
Reset
Register
within
the
MPC8641D
interrupt
controller.
5.10.2 SYSRESET~ Signal
The
VPX
SYSRESET~
signal
is
asserted
by
hardware
when
a
hard
reset
event
occurs
and
the
board
is
the
VPX
System
Controller
(SYS_CON).
The
duration
of
the
VPX
SYSRESET~
signal
is
at
least
10ms.
5.10.3 Machine Check Exception
MCP~
inputs
are
tied
high
and
are
not
used.
Table 5-13 Processor Interrupts
Priority
Interrupt
Cause
Recoverability
0
System Reset
Power on,
Hard Reset Input
Non-recoverable
1
Machine Check
MCP~ Input
Non-recoverable in most cases
2
System Reset
Soft Reset Input
Recoverable unless Machine Check
occurs
3
System
Management
Interrupt
SMI~ input
Recoverable unless Machine Check or
System Reset occurs
4
External Interrupt
INT~ input
Recoverable unless Machine Check or
System Reset occurs
