36 VMIVME-7807/VME-7807RC Hardware Reference Manual
.
When
either
of
these
fields
are
written
(either
by
a
single
32
‐
bit
write
or
separate
16
‐
bit
writes),
the
respective
timer
is
loaded
with
the
written
value
on
the
next
rising
edge
of
the
timer
clock,
regardless
of
whether
the
timer
is
enabled
or
disabled.
The
value
stored
in
this
register
is
also
automatically
reloaded
on
terminal
count
(or
timeout)
of
the
timer.
3.3.4 Timer 3 Load Count Register (TMRLCR3)
Timer
3
is
32
‐
bits
wide
and
obtains
its
load
count
from
the
Timer
3
Load
Count
Register
(TMRLCR3),
located
at
offset
0x14
from
the
address
in
BAR2.
The
mapping
of
bits
in
this
register
is
shown
in
When
this
field
is
written,
Timer
3
is
loaded
with
the
written
value
on
the
next
rising
edge
of
the
timer
clock,
regardless
of
whether
the
timer
is
enabled
or
disabled.
The
value
stored
in
this
register
is
also
automatically
reloaded
on
terminal
count
(or
timeout)
of
the
timer.
3.3.5 Timer 4 Load Count Register (TMRLCR4)
Timer
4
is
32
‐
bits
wide
and
obtains
its
load
count
from
the
Timer
4
Load
Count
Register
(TMRLCR4),
located
at
offset
0x18
from
the
address
in
BAR2.
The
mapping
of
bits
in
this
register
is
shown
in
When
this
field
is
written,
Timer
4
is
loaded
with
the
written
value
on
the
next
rising
edge
of
the
timer
clock,
regardless
of
whether
the
timer
is
enabled
or
disabled.
The
value
stored
in
this
register
is
also
automatically
reloaded
on
terminal
count
(or
timeout)
of
the
timer.
3.3.6 Timer 1 & 2 Current Count Register (TMRCCR12)
The
current
count
of
timers
1
&
2
may
be
read
via
the
Timer
1
&
2
Current
Count
Register
(TMRCCR12),
located
at
offset
0x20
from
the
address
in
BAR2.
The
mapping
of
bits
in
this
register
is
shown
in
Table 3-5 TMRLCR12 Bit Mapping
Field
Bits
Read or Write
Timer 2 Load Count
TMRLCR12[31..16]
R/W
Timer 1 Load Count
TMRLCR12[15..0]
R/W
Table 3-6 TMRLCR3 Bit Mapping
Field
Bits
Read or Write
Timer 3 Load Count
TMRLCR3[31..0]
R/W
Table 3-7 TMRLCR4 Bit Mapping
Field
Bits
Read or Write
Timer 4 Load Count
TMRLCR4[31..0]
R/W