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3465&3485-mfc.ib.rev4.doc 

page 16 of 22

 17/10/2007

 

MPEG-2 transport layer coding 

 
The MPEG-2 Transport Layer is defined in ISO/IEC DIS 13818-1 [1]. The Transport Layer for MPEG-2 data is 
comprised of packets having 188 Bytes, with one Byte for synchronisation purposes, three Bytes of header 
containing service identification, scrambling and control information, followed by 184 Bytes of MPEG-2 or 
auxiliary data. 
The framing organisation is based on the MPEG-2 transport packet structure. 
 

Channel coding 

To achieve the appropriate level of error protection required for cable transmission of digital data, a FEC based on 
Reed-Solomon encoding is used. In contrast to the Baseline System for satellite described in ETS 300 421, no 
convolutional coding is applied to cable transmission. Protection against burst errors is achieved by the use of Byte 
interleaving. 
 

Randomisation for spectrum shaping (Scrambling) 

The System input stream is organised in fixed length packets (see figure 2), following the MPEG-2 transport 
multiplexer. The total packet length of the MPEG-2 transport MUX packet is 188 Bytes. This includes 1 sync-word 
Byte (i.e. 47

HEX

).

 

The processing order at the transmitting side shall always start from the MSB (i.e. 0) of the sync 

word-Byte (i.e. 01000111). 
 
In order to comply with the System for satellite, (see ETS 300 421) and to ensure adequate binary transitions for 
clock recovery, the data at the output of the MPEG-2 transport multiplex is randomised. 
 
The polynomial for the Pseudo Random Binary Sequence (PRBS) generator is: 
 
1 + X

14 

+ X

15

 

 
Loading of the sequence 100101010000000" into the PRBS registers, is initiated at the start of every eight transport 
packets. To provide an initialisation signal for the de-scrambler, the MPEG-2 sync Byte of the first transport packet 
in a group of eight packets is bitwise inverted from 47

HEX

 to B8

HEX

.  

 
The first bit at the output of the PRBS generator is applied to the first bit of the first Byte following the inverted 
MPEG-2 sync Byte (i.e.B8

HEX

). To aid other synchronisation functions, during the MPEG-2 sync Bytes of the 

subsequent 7 transport packets, the PRBS generation continues, but its output is disabled, leaving these Bytes 
unrandomised. The period of the PRBS sequence shall therefore be 1,503 Bytes. 
 
The randomisation process is active also when the modulator input bit-stream is non-existent, or when it is non-
compliant with the MPEG-2 transport stream format (i.e. 1 sync Byte + 187 packet Bytes). This is to avoid the 
emission of an unmodulated carrier from the modulator. 
 

Reed-Solomon coding 

Following the energy dispersal randomisation process, systematic shortened Reed-Solomon encoding is performed 
on each randomised MPEG-2 transport packet, with T = 8. This means that 8 erroneous Bytes per transport packet 
can be corrected. This process adds 16 parity Bytes to the MPEG-2 transport packet to give a codeword (204, 188). 
 
NOTE: RS coding is applied also to the packet sync Byte, either non-inverted (i.e. 47

HEX

)

 

or inverted (i.e. B8

HEX

). 

 
Code Generator Polynomial: g(x) = (x+

λ

0

)(x+

λ

1

)(x+

λ

2

) ... (x+

λ

15

), where 

λ

 = 02

HEX

 

 
Field Generator Polynomial: p(x) = x

+ x

+ x

+ x

+ 1 

 
The shortened Reed-Solomon code is implemented by appending 51 Bytes, all set to zero, before the information 
Bytes at the input of a (255, 239) encoder; after the coding procedure these Bytes are discarded. 
 

Summary of Contents for MFC-3465

Page 1: ...nd manufactured in Australia IRT can be found on the Internet at http www irtelectronics com I R T Electronics Pty Ltd A B N 35 000 832 575 26 Hotham Parade ARTARMON N S W 2064 AUSTRALIA National Phon...

Page 2: ...panel connector diagrams 11 Operation 12 Front indicators 12 Maintenance storage 13 Warranty service 13 Equipment return 13 Characteristics of signal types 14 Coding characteristics 14 G 703 14 Synch...

Page 3: ...absence of a valid MPEG ASI input the MFC 3485 will transmit all ones IRT s 34XX series of adapters provide a modular approach to connecting between the different transport types The 34XX series find...

Page 4: ...sion of variable rates of DVB ASI to G 703 and for transport via Telecom circuits Block length indication and error detection Block diagrams MFC 3465 Alarms indications 188 BYTE BLOCK 204 BYTE BLOCK S...

Page 5: ...ed Data rate 34 368 Mb s Output 1 x ASI C Impedance 75 Level 800 mVp p Added PCR Jitter Less than 240nS Connectors BNC Power Requirements 28 Vac CT 14 0 14 or 16 Vdc Power consumption 5 VA Other Tempe...

Page 6: ...ale logic array The internal logic and functions of this IC are too complex to describe in detail and the following is intended as a guide to function only Data rates are byte stuffed here to bring th...

Page 7: ...function only Data loss detection If the input level is insufficient for correct operation or if more than 180 1 s occur in a row then data loss is deemed to have occurred Sync Error After 2 consecuti...

Page 8: ...5 feet MFC 3485 45 45 Mb s version OUT DS3 unshaped output for 225 feet MFC 3485 45 45 Mb s version Note Leave out on MFC 3485 34 34 Mb s version LK 3 LEFT Relay Alarm set to indicate on Loss of Signa...

Page 9: ...ge of unit and local supply voltage match and that correct rating fuse is installed for local supply Earthing Particular care should be taken to ensure that the frame is connected to earth for safety...

Page 10: ...K3 or Loss of Power MFC 3465 G 703 input This BNC input is terminated in 75 Ohms Input cable compensation is automatic for up to 450 feet of 75 Ohm coaxial cable Belden 8281 equivalent Input equalisat...

Page 11: ...following front panel and rear assembly drawings are not to scale and are intended to show relative positions of connectors indicators and controls only INPUT SYNC 204 188 DC MFC 3465 N140 INPUT SYNC...

Page 12: ...put as outlined below Front indicators Input loss alarm This LED lights when there is a loss of input signal or coding errors occur on the input stream Sync loss alarm This LED lights for at least 300...

Page 13: ...be extended by IRT only to the extent obtainable from the component supplier Equipment return Before arranging service ensure that the fault is in the unit to be serviced and not in associated equipme...

Page 14: ...transmission of variable data rates The data transfer is synchronised to the Byte clock of the MPEG transport stream The data to be transmitted are MPEG 2 transport packets The data signals are synchr...

Page 15: ...of 1 bits and 0 bits in the transmitted serial data stream The disparity characteristics of the code maintain DC balance Special characters are defined as extra code points beyond the need to encode a...

Page 16: ...ing of the sequence 100101010000000 into the PRBS registers is initiated at the start of every eight transport packets To provide an initialisation signal for the de scrambler the MPEG 2 sync Byte of...

Page 17: ...branches cyclically connected to the input Byte stream by the input switch Each branch is a First In First Out FIFO shift register with depth Mj cells where M 17 N I N 204 error protected frame length...

Page 18: ...to 8448 KHz 18 dB 8448 KHz to 12672 KHz 14 dB Electrical characteristics CCITT G 703 34368 Kb s Cable type Coaxial Impedance 75 Signal level 1 0 V Nominal pulse width 14 55 ns Code conversion HDB3 Pu...

Page 19: ...ut regard for the underlying data rate thus simplifying system design Note that the ASI signal is polarity sensitive Although most 270 Mb s SDI DA s and switchers will pass ASI signals the line driver...

Page 20: ...vices framing structure channel coding for 11 12 GHz satellite services ETS 300 429 Digital broadcasting systems for Television sound and data services framing structure channel coding and modulation...

Page 21: ...PGA Field Programmable Gate Array G 703 ITU CCITT recommendation G 703 HDB3 High Density Bi polar of order 3 IF Intermediate Frequency IRD Integrated Receiver Decoder ITU International Telecommunicati...

Page 22: ...04382 1 MFC 3465 circuit schematic G 703 to ASI converter 804382 2 MFC 3465 circuit schematic G 703 to ASI converter 804384 1 MFC 3485 circuit schematic ASI to SPI converter 804384 2 MFC 3485 circuit...

Page 23: ...49 50 51 52 53 58 59 47 48 1 U5 BB1 RP2 U12 39 79 80 81 83 XTAL1 5 32a b TP1 78 Dvdd 4 20 33 40 45 63 5 1K 1 5 6 7 28 CKW 10 5 4 22 23 ENANot 25 5 Avdd 54 5 5 5 5 5 21a b 22a b 23a b 24a b 25a b 26a b...

Page 24: ...WING No COPYRIGHT ARTARMON NSW AUSTRALIA 2064 A3 U5 2 28 10 98 5 18 20 11 T7295 10 38 37 U3 28ab 27ab MFC 3465 G703 TO ASI CONVERTER 14 15 16 RNDATA RPDATA RCLK 12 2 EQ 9 1 4 5 3 6 13 RIN 7 8 44 39 2...

Page 25: ...8 7 7 7 7 6 6 6 8 8 6 5 2 3 10 11 14 13 2 3 10 11 14 13 7 1 9 15 1 9 15 61 62 73 71 72 70 69 66 67 65 64 10b 10a 9b 9a 8b 8a 7b 7a 6b 6a 5b 5a 4b 4a 3b 3a 1b 1a 11b 11a 12b 12a 31a b 1Psync 1Dvalid 1C...

Page 26: ...38 35 2 2 28 10 98 TO SHT 1 Phase DDSclock Dclockin 4 3 2 1 8 5 6 7 Q Dvdd MAX961 5 22 23 25 4 DS3 E3 TXLEV TRING TTIP RCLK RLOOP TAOS GND GND RPDATA RNDATA 1 2 5 10 21 27 28 24 3 6 26 12 T7296 11 8...

Page 27: ...S RCLK RLOOP TAOS GND GND RPDATA RNDATA 1 2 5 10 21 27 28 24 3 6 26 12 T7296 11 8 7 9 U4 28ab 27ab MFC 3485 ASI TO G703 CONVERTER 3 17 RCLKO3 RNEG ALARM 3 8 1 5 14a 14b 5 5 TO LED1 TO LED2 36 U5 XTAL2...

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