AN4536 Application Note Rev. 2.0 1/2014
24
Freescale Semiconductor
OTP Overview
All interrupts are masked by default, therefore the ECC interrupt should be unmasked after fuses are programmed,
with ECC enabled, to determine if single or double bit errors exist in any of the banks. The location of the error bits
may be read from the registers described in
Table 34
.
Table 36. OTP ECC DE1 and 2 Register Description
Bit
Name
Default
Description
OTP ECC DE1
0
ECC1_DE
0
Dual error detection in fuse bank 1
0 = No single error detected
1 = Single error detected
1
ECC2_DE
0
Dual error detection in fuse bank 2
0 = No single error detected
1 = Single error detected
2
ECC3_DE
0
Dual error detection in fuse bank 3
0 = No single error detected
1 = Single error detected
3
ECC4_DE
0
Dual error detection in fuse bank 4
0 = No single error detected
1 = Single error detected
4
ECC5_DE
0
Dual error detection in fuse bank 5
0 = No single error detected
1 = Single error detected
7:5
RSVD
0
Reserved
OTP ECC DE2
0
ECC6_DE
0
Dual error detection in fuse bank 6
0 = No single error detected
1 = Single error detected
1
ECC7_DE
0
Dual error detection in fuse bank 7
0 = No single error detected
1 = Single error detected
2
ECC8_DE
0
Dual error detection in fuse bank 8
0 = No single error detected
1 = Single error detected
3
ECC9_DE
0
Dual error detection in fuse bank 9
0 = No single error detected
1 = Single error detected
4
ECC10_DE
0
Dual error detection in fuse bank 10
0 = No single error detected
1 = Single error detected
7:5
RSVD
0
Reserved
