GEMINI
Issue 1
Section 7
MCUK991001G8
Revision 0
– 28 –
Technical Guide
7.2.3 Memory Interface
The memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait states to memory
access. The memory interface allows between 0 and 7 wait states to be added. The ROM area is hardware write protected, a
FLASH write enable bit in the ROM wait state configuration register can be used to enable write access the ROM area.
7.2.4 Interrupt Handler
The ARM CPU has two interrupts, FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.
Gemini has 11 interrupt sources. The Interrupt handler assigns priorities to these interrupts and routes them to either the FIQ
or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked
interrupt, if the CPU is in sleep mode.
For GD30/GD50, the FIQ interrupt is reserved for the power supply fail priority interrupt.
CPU Memory MAP
Device Name
Start address
Size
Use
Bus width
ROM
0000:0000
2M
FLASH 2 Mbytes
16 bits
RAM
0020:0000
2M
Static RAM 256 kbytes
8 bits
BUS CNTRL
0040:0000
1M
wait state registers
16 bits
API RAM
0050:0000
8k
CPU/DSP shared ram
16 bits
APIC
0050:4000
1k
CPU/DSP interface controller
16 bits
TPU RAM
0050:4400
1k
GSM timer Micro-code RAM
16 bits
SIM
0050:4800
1k
SIM interface
16 bits
TSP
0050:4C00
1k
Timed Serial port
16 bits
INTH
0050:5000
1k
Interrupt controller
16 bits
TPU REG
0050:5400
1k
GSM timer registers
16 bits
CLKM
0050:5800
1k
Clock control module
16 bits
TIMER
0050:5C00
1k
software timers
16 bits
APIF
0050:6000
1k
ARM peripheral interface
16 bits
UWIRE
0050:6400
1k
Synchronous Serial port
16 bits
ARMIO
0050:6800
1k
Keypad, buzzer, LCD & I/O
16 bits
8251
0050:6C00
1k
UART
16 bits
CS2
0060:0000
2M
LCD driver
8 bits
nCS0
0080:0000
2M
Extended I/O
8 bits
nCS1
00A0:0000
2M
not used
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Interrupt Level Assignments
Interrupt source
Description
Interrupt detection
IRQ_TIM1
Buzzer timer
Edge sensitive
IRQ_TIM2
Operating system timer
Edge sensitive
IRQ_API
DSP Interface interrupt
Rising Edge sensitive
IRQ_EXT
Power supply fail interrupt
Low Level sensitive
IRQ_USART
UART Interrupt
Level sensitive
IRQ_ARMIO
Keypad Interrupt
Low for 1 clock period
IRQ_FRAME
Frame Interrupt
Edge sensitive
IRQ_PAGE
Page Interrupt
Edge sensitive
IRQ_TIM_GSM
GSM Timer (TPU) Interrupt
Edge sensitive
IRQ_TSP
Timed serial port Interrupt
Edge sensitive
IRQ_SIM
SIM Interrupt
Level sensitive
IRQ_F_USART
Fast interrupt from USART
Level sensitive
IRQ_RSS
Radio subsystem interrupt
Edge sensitive
