Rastergraf
Programming On-board Devices 3-11
3.4 Synchronous Graphics RAM (SGRAM)
The display memory chips are expressly designed for high speed graphics
applications. These devices are called Synchronous Graphics RAMs
(SGRAMs).
The SGRAM replaces the previously used Video RAM, which had a two-
port design with separate video output that drove an external RAMDAC.
While the VRAM was potentially able to supply substantially better
performance than the SGRAM, the price pressures of the PC market made
it too expensive.
The SGRAM is a single port device: the random access and video refresh
access data all come out on the same data lines, and are routed through the
graphics controller. The SGRAM can be built on the same fab line as
SDRAM, and, by adding a few graphics-oriented features, combined with
building the RAMDAC into the graphics controller, provides a more cost
effective solution at a small performance penalty.
The video refresh reads a block of video data into a FIFO in the Borealis
which eventually passes the data to the on-chip RAMDAC. Depending on
the horizontal line pixel count, the video refresh transfer operation may
have to be repeated several times during the raster line time to keep the
FIFO filled. The SGRAM is available for random access operations at all
other times. There is a small additional overhead time for memory refresh,
which occurs about once every 15 us. The SGRAM availability for
random access is about 75%. The Borealis uses 32 Mb Samsung
K4G323222A-2x512K x 32 SGRAM.
Write-per-bit Registers
SGRAM has a write-per-bit feature that allows bit planes to be selectively
write enabled. This feature allows the Borealis to perform write operations
instead of read-modify-write operations, which can be a significant
performance enhancement. When updated, the Borealis write-per-bit
register contents are automatically stored in the SGRAM using the
persistent write-per-bit function.
SGRAM Color Register and Block Fill Special Function
The Borealis can use the SGRAM block write and color register special
functions. The color register is used in conjunction with the SGRAM
block fill mode to enable up to 8 adjacent 32-bit locations in the SGRAM
to be written in one cycle. In this way, one can quickly replicate 1-D and
2-D patterns in memory at many times the single pixel rate. Using block
write, up to 128 (16 byte data bus * 8 locations/block) 8-bit pixels can be
written in each 10 ns page mode cycle, resulting in a 12.8 Gpixel/sec FILL
time.
