Sejin Electron SKR-2006, User Manual

3 

1.0 ELECTRRICAL 

   1.1 Power 
      1.1.1 5VDC

±

10%, 40mA .

2.0 POWER ON ROUTINE 

   2.1 Power on Reset-POR- 
            2.2.1 The keyboard will perform a power on reset -POR- within a minimum of   
                      150

㎳

  and a maximum of 2

㎳

. 

   2.2 Basic Assurance Test -BAT-   

            2.2.1 The keyboard will conduct a basic assurance test -BAT- of the processor.   
            2.2.2 Turn the LED's(if so equipped) on at the beginning of the test and off at   
           the end of the test. 

            2.2.3 Transmit the completion code AAH if the test was successful. 
            2.2.4 The -BAT- takes a maximum of 500

㎳

. During this time all activity on the   

           clock and data lines will be ignored. 
            2.2.5 The completion code will be transmitted within 450

㎳

  and not more than   

           2.5sec after -POR-, and within 500

㎳

  after a reset command is acknowledge. 

3.0 DATA TRANSMISSION 

      3.1 Clock and Data lines 

            3.1.1 The click and data lines are used for communication in both directions   
                      between the system and the keyboard. These lines are driven by an open   
                      collector device which allows either the system or the keyboard to force the   

           line to an inactive(low)level. When no communication is occurring both lines  
                      are active(high). 
            3.1.2 The keyboard provides the clocking signals used to clock serial data to and   

           from the keyboard. 
            3.1.3 The data line is used for transmission of data by both the system and the   
                      keyboard. The system issues a`Request to Send' -RTS- by pulling the data line   
                      to logic`0'. 

   3.2 DATA format 
            3.2.1 The data protocol is an 11-bit data stream that consists of 1 start   
           bit(always Logic 0), 8 data bits(least significant bit to most significant bit  

           respectively), 1 odd parity bit, and 1 stop bit(always Logic 1). 
            3.2.2 See figure 14 for graphic representation of these signals. 
      3.3 Keyboard to System line protocol 

            3.3.1 Keyboard checks clock line, if Logic 1 continue, if Logic 0 store keystrokes   
           if protocol is 11-bit(inhibited); otherwise check for possible reset. 
            3.3.2 Keyboard checks data line, if Logic 1 continue, if Logic 0 prepare to receive   
           data from system if protocol is 11-bit; otherwise store keystrokes(inhibited). 

            3.3.3 Keyboard transmits data. While transmitting in the 11-bit protocol, the   
                      keyboard checks the clock line for logic level 1 at least every 60 

㎲

.(See line   

           contention below). 
   3.4 Line Contention 

            3.4.1 The system may interrupt keyboard data transmission at any time up to the   
           10th clock by pulling the system must receive the keyboard data.   
   3.5 Line Contention 

            3.5.1 System inhibits keyboard by lowering clock line to logic 0 for a minimum of   
                      60

㎲

.  

            3.5.2 System requests transmission by lowering the data to logic 0(-RTS-)and   
           allows the clock line to go active.