BlueNRG-1 peripheral
driver examples
UM2264
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DocID030868 Rev 1
Timer/Counter 1 interrupts on reload are enabled for MFTX1. Interrupt routines toggle LED
DL1 for MFTX2.
Mode 2
(dual-input capture mode): Timer/Counter 1 counts down with the selected clock
and TnA and TnB pins function as capture inputs. Transitions received on the TnA and TnB
pins trigger a transfer of timer content to the TnCRA and TnCRB registers, respectively.
Timer/Counter 2 counts down with selected clock and can generate an interrupt on
underflow.
In this example, MFTX1 is used. The CPU clock is selected as the clock signal for
Timer/Counter 1 and a Prescaled clock is used as the clock source for Timer/Counter 2.
Sensitivity to falling edge is selected for TnA and TnB inputs; counter preset to 0xFFFF is
disabled for both inputs.
The IO2 pin is internally connected to TnA input (MFTX1) and the IO3 pin is internally
connected to TnB input (MFTX1).
Interrupts TnA and TnB are enabled and triggered by transitions on pins TnA and TnB,
respectively. The interrupt routine records the value of TnCRA or TnCRB and calculates
the period of the input signal every second interrupt.
Interrupt TnC is enabled and is triggered on each underflow of Timer/Counter1; it
increments the underflow counter variables used to calculate the input signal period.
LED DL1 is toggled ON if a frequency of about 1 kHz is detected on IO2, and LED DL2 is
toggled ON if a frequency of about 10 kHz is detected on IO3.
Mode 3
(dual independent timer/counter): the timer/counter is configured to operate as a
dual independent system timer or dual external-event counter. Timer/Counter 1 can also
generate a 50% duty cycle PWM signal on the TnA pin, while the TnB pin can be used as
an external-event input or pulse-accumulate input, and serve as the clock source to either
Timer/Counter 1 or Timer/Counter 2. Both counters can also be operated from the
prescaled system clock.
In this example MFTX1 is used. The CPU clock is selected as the clock signal for
Timer/Counter 1, while Timer/Counter 2 uses an external clock on TnB pin. Sensitivity to
rising edge is selected for TnB input. Timer/Counter 1 is preset and reloaded to 5000, so
the frequency of the output signal is 1 kHz. Timer/Counter 2 is preset and reloaded to 5.
The IO3 pin is internally connected to TnA input (MFTX1), while the IO2 pin is configured
as output and configured as the PWM output from Timer/Counter 1.
The LED DL1 is toggled in the main program according to a variable which is changed in
TnD interrupt routine. Interrupt TnA and TnD are enabled and are triggered on the
underflow of Timer/Counter1 and Timer/Counter2 respectively.
Mode 4
(input-capture plus timer): is a combination of mode 3 and mode 2, and makes it
possible to operate Timer/Counter 2 as a single input-capture timer, while Timer/Counter 1
can be used as a system timer as described above.
In this example, MFTX1 is used. The CPU clock is selected as the input clock for
Timer/Counter 1 and Timer/Counter 2. Automatic preset is enabled for Timer/Counter 2.
The IO2 pin is internally connected to the TnB input (MFTX1), while the IO3 pin is
configured as the output and configured as the PWM output from Timer/Counter 1.
Interrupt TnA is enabled and triggered on the underflow of Timer/Counter1; it sets a new
value in the TnCRA register. Interrupt TnB in enabled and triggered when a transition on
TnB input (input capture) is detected; it saves the TnCRB value. Interrupt TnD in enabled
and it triggered on the underflow of Timer/Counter2.