Firmware
16
SLLU216 – July 2019
Copyright © 2019, Texas Instruments Incorporated
SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide
The TCAN4550-Q1 contains a 2-kB block of memory used for sending and receiving CAN messages
called the Message RAM (MRAM). This memory must be allocated by the system designer to define non-
overlapping memory sections that holds the various message related elements. The TCAN4550-Q1 does
not perform any check on the MRAM layout to ensure a valid configuration free of overlapping sections. It
is critical for the system designer to verify the MRAM configuration is correct in order to avoid
unanticipated behavior.
The MRAM can be configured into 7 sections, all of which are optional and without any order or
sequencing restrictions.
There are two sections that can be used to define the 11-bit and 29-bit ID Filter elements. These are used
to filter any incoming CAN messages as relevant, or non-relevant, for this node.
There are two sections that can be used as Receive FIFOs (RX FIFO 0 and RX FIFO 1). These store the
incoming CAN messages but are not the only method of handling received messages.
RX Buffers can also be setup as another section that holds specific CAN messages, such as those
containing specific message identifiers. These are not FIFOs and if new data is received into the buffer
before the old data is read, the previous data is lost. RX Buffers and RX FIFOs can be setup and used at
the same time if desired.
A Transmit Event FIFO section can be created to store message transmit event messages. These
elements are generated by the TCAN4550-Q1 when transmitting a message are are for the
microcontroller to read and know the status of a sent message.
TX Buffers are the final section that can be setup that holds the messages to be transmitted. When a
message is to be sent, the data must first be loaded into the buffer before the transmission request can be
made to the TCAN4550-Q1 by the microcontroller to start the transmission. The controller then tries to
send the messages on the bus at the first available opportunity given the arbitration rules and message
identifier priority level as compared with the other messages being transmitted from other nodes at that
moment.
3.2
Sending and Receiving CAN Messages
In order to transmit a message with the TCAN4550-Q1, the following should be complete:
1. Ensure that the TCAN4550-Q1 is in standby mode (register 0x0800[7:6] = 0'b01). This forces M_CAN
into INIT mode.
2. Set the M_CAN CCR register to allow for configuration. Set CCE and INIT bits if not already set.
NOTE: The CSR bit reads back a 1 when in standby mode, but the user MUST write a 0 to this bit
when doing a read-modify-write; otherwise, CAN communication fails.
3. If CAN FD and Bit Rate Switching (BRS) support is desired, it must be globally enabled via the FDF
and BRS bits in the CCR register during configuration. See the device datasheet for more information
about this register.
4. Any desired device features should be configured such as the watchdog timer, etc.
5. CAN timing information must be set.
6. The MRAM sections should be configured and initialized with any data.
7. Put the TCAN4550-Q1 device into "normal" mode (register 0x0800[7:6] = 0'b10) to turn on the
transceiver and enable the CAN core for transmission.
Once these steps are complete, the microcontroller is able to transmit a message by writing to the TX
Buffer and then requesting a message be sent by writing to the TXBAR register.
3.2.1
Sending a message
To send a message, it must first be written into the TX Buffer. A more detailed example of this process
can be found in the section 4.3.1 of the
TCAN45xx Software User's Guide
1. Check the TX FIFO/Queue Status register (TXFQS: 0x10C4) bits [5:0] to make sure the free level is
greater than 0 (meaning that at least 1 buffer is available) and that TFQF bit is set to 0.
2. Read TXFQS.TFQPI to get which index the message should be loaded into.
3. Calculate the memory offset to determine the start address in the MRAM memory.
