DNx-SL-514 Synchronous Serial Interface Board
Chapter 1
10
Introduction
May 2018
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© Copyright 2018
United Electronic Industries, Inc.
Master clock source
. Master ports can assign which clock source to use to
derive their baud rate clock:
•
derived from 66 MHz system clock (default)*
•
derived from onboard PLL*
NOTE:
*In most cases the baud rate should be derived from the 66 MHz system
clock, which is the default configuration. However, in some instances
when programming baud rates greater then 1 MHz, users may choose
to use the onboard PLL to derive the clock rate, which can yield a finer
frequency granularity.
For either master clock source, the baud rate is generated by dividing down the
clock source. When using the 66 MHz system clock, this will result in dividing
down from 33 MHz. If your application requires a baud rate that is not evenly
divisible by 33 MHz, the actual baud you will get is one that is as close as
possible to your requested rate
and
evenly divisible by 33 MHz. If your
application requires finer granularity, the PLL can be used.
1.7.3
FIFO
Operation &
Timestamping
Data storage for each master controller is provided by a 2048 x 32-bit FIFO. This
supports storage for 1024 received words and allows each word to be tagged
with a timestamp, if the timestamping option is enabled. If timestamping is not
enabled, all 2048 locations can be used for data. Received words are stored in
the FIFO until read by CPU; users can program master data transfers based on
a programmable FIFO watermark, FIFO timeout, or FIFO overrun.
Data storage for each slave controller is provided by a 1024 x 32-bit FIFO. Users
can store up to 1024 words in the slave output FIFO at a time.
