DNx-SL-514 Synchronous Serial Interface Board
Chapter 3
22
Programming with the Low-Level API
May 2018
www.ueidaq.com
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© Copyright 2018
United Electronic Industries, Inc.
Table 3-2
SL-514
Configuration Options
Configuration
Parameter
Options
ch_cfg
The following #define settings can be logically ORed together for the channel
configuration (
ch_cfg)
parameter
:
•
L514CFG_SLAVE_EN
: enable slave port for the channel
•
L514CFG_MASTER_EN
: enable master port for the channel
•
L514CFG_MASTER_TS
: add timestamp to the master data
•
L514CFG_OUTPUTS_TERMN
: enable termination on channel outputs
•
L514CFG_INPUTS_TERMN
: enable termination on channel inputs
•
L514CFG_SLAVE_DATA_EN
: enable line drive Tx
•
L514CFG_MASTER_CLK_EN
: enable line drive Rx
•
L514CFG_SLAVE_Tprm
: enable slave T parameters (0 = use defaults)
•
L514CFG_MASTER_Tprm
: program master T parameters (0 = use defaults)
flags
<Reserved>
clock_source
Sets clock source to use to derive master clock (for baud):
•
L514CFG_CLK_BASE
: use system 66MHz clock and divide it
•
L514CFG_CLK_PLL
: use on-board PLL as a clock source
baud_rate
uint32 300 baud to 1.3 Megabaud (uint32)
m_word_sz
master 3 to 32 bits in the word (uint32)
m_debounce
master debouncing settings:
• 0=bypass
• 1 thru 15 = 4 thru 18, 15 ns clocks,
(i.e., programming a “1” results in 4*15ns, or ~60 ns debouncing delay)
m_trigger
master trigger source that allows data to start transmission:
•
L514CFG_TRIG_IMM
: start immediately after enable, transmit when the
data is in the buffer
•
L514CFG_TRIG_GLOBAL
: wait for the global trigger to start
m_Tv
master tv time delay: see Figure 1-3 on page 8 and refer to Section 1.7.2 on page 9
for more information.
m_Tp
master pause time delay setting: see Figure 1-3 on page 8 and refer to Section 1.7.2
on page 9 for more information.
m_Tm
master transfer timeout/monoflop time setting: see Figure 1-3 on page 8 and refer to
Section 1.7.2 on page 9 for more information.
s_word_sz
slave 3 to 32 bits in the word (uint32)
s_debounce
slave debouncing settings:
• 0=bypass
• 1 thru 15 = 4 thru 18, 15 ns clocks,
(i.e., programming a “1” results in 4*15ns, or ~60 ns debouncing delay)
