Special Registers
EPM-32 Reference Manual
48
Revision Indicator Register
REVIND (READ ONLY) 1D1h (or 1E1h via CMOS Setup)
D7
D6
D5
D4
D3
D2
D1
D0
PC4
PC3
PC2
PC1
PC0
REV2
REV1
REV0
This register is used to indicate the revision level of the EPM-32.
Bit
Mnemonic
Description
D7-D3
PC4-PC0
Product Code
— These bits are hard-coded to represent the product type. The
EPM-32 always reads as 11000. Other codes are reserved for future products.
PC4 PC3 PC2 PC1 PC0
Product Code
1
1
0
1
0
EPM-32
Note:
These bits are read-only.
D2-D0
REV2-REV0
Revision Level
— These bits represent the EPM-32 circuit revision level.
REV2
REV1 REV0
Revision Level
0
0
0
Initial product release, EPM-32c, p, v
1
0
0
EPM-32e, t
Note:
These bits are read-only.
Watchdog Timer Hold-Off Register
WDHOLD (WRITE ONLY) 1D1h (or 1E1h via CMOS Setup)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
A watchdog timer circuit is included on the EPM-32 board to reset the CPU and/or generate a
NMI if proper software execution fails or a hardware malfunction occurs. The watchdog timer is
controlled by the SCR and JSR.
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (1000 ms minimum). Writing 5Ah to WDHOLD resets the
watchdog timeout period.