SPX-5 Reference Manual
12
Base Board SPI Registers
The following tables describe the SPI control and data registers of the EBX-11 Rev. 6.00
and later. This is the standard set of SPI registers for VersaLogic CPU boards with an
SPX interface. See the appropriate base-board reference manual for details and updates.
SPICONTROL (READ/WRITE) 1D8h
D7
D6
D5
D4
D3
D2
D1
D0
CPOL
CPHA
SPILEN1
SPILEN0
MAN_SS
SS2
SS1
SS0
Table 7: SPI Control Register 1 Bit Assignments
Bit
Mnemonic
Description
D7
CPOL
SPI Clock Polarity
–
Sets the SCLK idle state.
0 = SCLK idles low
1 = SCLK idles high
D6
CPHA
SPI Clock Phase
–
Sets the SCLK edge on which valid data will be read.
0 = Data read on rising edge
1 = Data read on falling edge
D5-D4
SPILEN
SPI Frame Length
–
Sets the SPI frame length. This selection works in
manual and auto slave select modes.
SPILEN1 SPILEN0 Frame Length
0
0
8-bit
0
1
16-bit
1
0
24-bit
1
1
32-bit
D3
MAN_SS
SPI Manual Slave Select Mode
–
This bit determines whether the slave
select lines are controlled through the user software or are automatically
controlled by a write operation to SPIDATA3 (1DDh). If MAN_SS = 0, then the
slave select operates automatically; if MAN_SS = 1, then the slave select line
is controlled manually through SPICONTROL bits SS2, SS1, and SS0.
0 = Automatic, default
1 = Manual
D2-D0
SS
SPI Slave Select
–
These bits select which slave select will be asserted. The
SSx# pin on the base board will be directly controlled by these bits when
MAN_SS = 1.
SS2 SS1 SS0 Slave Select
0
0
0
None, port disabled
0
0
1
SPX Slave Select 0, J17 pin-8
0
1
0
SPX Slave Select 1, J17 pin-9
0
1
1
SPX Slave Select 2, J17 pin-10
1
0
0
SPX Slave Select 3, J17 pin-11
1
0
1
On-Board A/D Converter Slave Select
1
1
0
On-Board Digital I/O Ch 0-Ch 15 Slave Select
1
1
1
On-Board Digital I/O Ch 16-Ch 31 Slave Select
A
