Hardware Reference Guide
SST-DN3-PCI-1 and SST-DN3-PCI-2
32
Hardware
Register
Details
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.1, Document #: 715-0083, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
3.3 DN3 Card Configuration Registers
This section provides hardware register details for the card.
3.3.1 Host Register Layout
Each channel has its own set of registers, located in I/O space.
Note
Upon card power up, or after a physical reset from the system, it
typically takes 1 second for the channel to initialize (though it is
recommended that applications wait up to 2 seconds). Initialization can
be confirmed by monitoring the LEDs or by reading the FamilyID
register, as described in Section C.1.1,
Verify Card Presence
.
Table 6: Host Register Layout
The following “offsets” are offsets from the base address. An “X” means that the bit is reserved
(writing to it will result in undefined behavior).
Offset
Register
Bit Name
Name
7
6
5
4
3
2
1
0
00h Control CardRun
(r/w)
MemEn
(r/w)
IntEn
(r/w)
WdTout
(read)
HostIrq1
(r/w)
HostIrq0
(r/w)
CardIrq1
(r/w)
CardIrq0
(r/w)
01h
(rd)
AddrMatch
X X X X X X X X
02h
BankAddress
0 0 0
BA16
BA15
BA14
BA13
BA12
03h
BankSize WS19 WS18 WS17 WS16 WS15 WS14 WS13 WS12
04h HostIrq
(r/w)
X X X X X X X X
05(rd) LedReg
(read)
X X
PwrRed
PwrGrn
HealthRed
HealthGrn
CommRed
CommGrn
06h Debug
(r/w)
X X X X X X X X
07
(rd)
HDR
(FamilyID)
HostDataReg (written by CPU)
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