3-2
Z380
™
U
SER
'
S
M
ANUAL
DC-8297-03
Z
ILOG
3.2 DECODER DIRECTIVES
The Decoder Directive is not an instruction, but rather a
directive to the instruction decoder. The instruction de-
coder may be directed to fetch an additional byte or word
of immediate data or address with the instruction, as well
as tagging the instruction for execution in either Word or
Long Word mode. Since the Z80 CPU architecture’s ad-
dressing convention in the memory is “least significant
byte first, followed by more significant bytes,” it is possible
to have such instructions to direct the instruction decoder
to fetch additional byte(s) of address information or imme-
diate data to extend the instruction.
All eight combinations of the two options are supported, as
shown below. Instructions which do not support decoder
directives are assembled by the instruction decoder as if
the decoder directive were not present.
■
DDIR W
Word mode
■
DDIR IB,W
Immediate byte, Word mode
■
DDIR IW,W
Immediate Word, Word mode
■
DDIR IB
Immediate byte
■
DDIR LW
Long Word mode
■
DDIR IB,LW
Immediate byte, Long Word mode
■
DDIR IW,LW
Immediate Word, Long Word
mode
■
DDIR IW
Immediate Word
The IB decoder directive causes the decoder to fetch an
additional byte immediately after the existing immediate
data or direct address, and in front of any trailing opcode
bytes (with instructions starting with DD-CB or FD-CB, for
example).
Likewise, the IW decoder directive causes the decoder to
fetch an additional word immediately after the existing
immediate data or direct address, and in front of any
trailing opcode bytes.
Byte ordering within the instruction follows the usual con-
vention; least significant byte first, followed by more signifi-
cant bytes. More-significant immediate data or direct
address bytes not specified in the instruction are read as
all zeros by the processor.
The W decoder directive causes the instruction decoder to
tag the instruction for execution in Word mode. This is
useful while the Long Word (LW) bit in the Select Register
(SR) is set, but 16-bit data manipulation is required for this
instruction.
The LW decoder directive causes the instruction decoder
to tag the instruction for execution in Long Word mode.
This is useful while the LW bit in the SR is cleared, but 32-
bit data manipulation is required for this instruction.
3.3 NATIVE MODE AND EXTENDED MODE
The Z380 CPU can operate in either Native or Extended
mode, as a way to manipulate addresses.
In Native mode (the Reset configuration), the Program
Counter only increments across 16 bits, and all stack Push
and Pop operations manipulate 16-bit quantities (two
bytes). Thus, Native mode is fully compatible with the Z80
CPU’s 64 Kbyte address space and programming model.
The extended portion of the Program Counter (PC31-
PC15) is forced to 0 and program address location next to
0000FFFFH is 00000000H in this mode. This means in
Native mode, program have to reside within the first 64
Kbytes of the memory addressing space.
In Extended mode, however, the PC increments across all
32 bits and all stack Push and Pop operations manipulate
32-bit quantities. Thus, Extended mode allows access to
the entire 4 Gbyte address space. In both Native and
Extended modes, the Z380 CPU drives all 32 bits of the
address onto the external address bus; only the PC incre-
ments and stack operations distinguish Native from Ex-
tended mode.
Note that regardless of Native or Extended mode, a 32-bit
address is always used for the data access. Thus, for data
reference, the complete 4 Gbytes of memory area may be
accessed. For example:
LD
BC, (HL)
uses the 32-bit address value stored in HL31-HL0 (HLz
and HL) as a source location address. However, on Reset,
the HL31-HL16 portion (HLz) initializes to 00H. Unless HLz
is modified to other than 00H, operation of this instruction
is identical to the one with the Z80 CPU. Modifying the
extended portion of the register is done either by using a
32-bit load instruction (in Long Word mode, or with DDIR
LW instructions), or using a 16-bit load instruction with
SWAP instructions.
