5-11
Z380
™
U
SER
'
S
M
ANUAL
Z
ILOG
DC-8297-03
5.5.6 8-Bit Manipulation, Rotate and Shift
Group
Instructions in this group (Table 5-11) test, set, and reset
bits within bytes, and rotate and shift byte data one bit
position. Bits to be manipulated are specified by a field
within the instruction. Rotate can optionally concatenate
the Carry flag to the byte to be manipulated. Both left and
right shifting is supported. Right shifts can either shift 0 into
bit 7 (logical shifts), or can replicate the sign in bits 6 and
7 (arithmetic shifts). All these instructions, Set Bit and
Reset Bit, set the CPU flags according to the calculated
result; the operand can be a register or a memory location
specified by the Indirect Register or Indexed addressing
mode.
The RLD and RRD instructions are provided for manipulat-
ing strings of BCD digits; these rotate 4-bit quantities in
memory specified by the Indirect Register. The low-order
four bits of the accumulator are used as a link between
rotation of successive bytes.
Table 5-11. Bit Set/Reset/Test, Rotate and Shift Group
Instruction Name
Format
A
B
C
D
E
H
L
(HL)
(IX+d) (IY+d)
Bit Test
BIT dst
√
√
√
√
√
√
√
√
√
√
Reset Bit
RES dst
√
√
√
√
√
√
√
√
√
√
Rotate Left
RL dst
√
√
√
√
√
√
√
√
√
√
Rotate Left Accumulator
RLA
√
Rotate Left Circular
RLC dst
√
√
√
√
√
√
√
√
√
√
Rotate Left Circular (Accumulator)
RLCA
√
Rotate Left Digit
RLD
√
Rotate Right
RR dst
√
√
√
√
√
√
√
√
√
√
Rotate Right Accumulator
RRA
√
Rotate Right Circular
RRC dst
√
√
√
√
√
√
√
√
√
√
Rotate Right Circular (Accumulator)
RRCA
√
Rotate Right Digit
RRD
√
Set Bit
SET dst
√
√
√
√
√
√
√
√
√
√
Shift Left Arithmetic
SLA dst
√
√
√
√
√
√
√
√
√
√
Shift Right Arithmetic
SRA dst
√
√
√
√
√
√
√
√
√
√
Shift Right Logical
SRL
√
√
√
√
√
√
√
√
√
√
5.5.7 16-Bit Manipulation, Rotate and Shift
Group
Instructions in this group (Table 5-12) rotate and shift word
data one bit position. Rotate can optionally concatenate
the Carry flag to the word to be manipulated. Both left and
right shifting is supported. Right shifts can either shift 0 into
bit 15 (logical shifts), or can replicate the sign in bits 14 and
15 (arithmetic shifts). The operand can be a register pair or
memory location specified by the Indirect Register or
Indexed addressing mode, as shown below.
Table 5-12. 16-Bit Rotate and Shift Group.
Destination
Instruction Name
Format
BC
DE
HL
IX
IY
(HL)
(HL)
(IX+d) (IY+d)
Rotate Left Word
RLW dst
√
√
√
√
√
√
√
√
√
Rotate Left Circular Word
RLCW dst
√
√
√
√
√
√
√
√
√
Rotate Right Word
RRW dst
√
√
√
√
√
√
√
√
√
Rotate Right Circular Word
RRCW dst
√
√
√
√
√
√
√
√
√
Shift Left Arithmetic Word
SLAW dst
√
√
√
√
√
√
√
√
√
Shift Right Arithmetic Word
SRAW dst
√
√
√
√
√
√
√
√
√
Shift Right Logical Word
SRLW
√
√
√
√
√
√
√
√
√
