ACCES I/O Products, Inc.
MADE IN THE USA
PCIe-ADIO16-16F Family Manual
7
Rev B3d
Base Clock:
Reading this 32-bit register returns the speed (in Hertz) of the clock used to generate ADC Start Conversions. Typical value is 50Million (50MHz), but for
broadest compatibility software should always read this register during init, and always use the read value when calculating what, if any, divisors to write to the
ADC Rate Divisor, DAC Waveform Rate Divisor, and Watchdog timeout registers.
DAC 4-20mA mode, 8 of 32-bit Memory BAR[1]Read 32-bits only
bit D31 through D4
D3
D2
D1
D0
Name UNUSED
DAC3 current mode only
DAC2 current mode only
DAC1 current mode only
DAC0 current mode only
If a bit is set then that DAC has current-mode output (4-20mA typ) installed and the DAC should only be configured for the 0-5V output range.
ADC Base Clock, C of 32-bit Memory BAR[1]Read Only 32-bits only
ADC Base Clock: Reading this 32-bit register returns the speed (in Hertz) of the clock used to generate ADC Start Conversions. Typical value is 125Million (125MHz), but for
broadest compatibility software should always read this register during init, and always use the read value when calculating what, if any, divisor to write to the
ADC Rate Divisor register.
ADC Rate Divisor, 10 of 32-bit Memory BAR[1]Read/Write 32-bits only
ADC Rate Divisor: Write a 32-bit divisor to the ADC Rate Divisor register to control the speed at which ADC Conversions occur in selected ADC Conversion Start Modes.
Actual ADC Start Rate (Hz) = ADC Base Clock ÷ ADC Rate Divisor
ADC Rate Divisor = integer(ADC Base Clock ÷ Target ADC Start Rate)
In ADC Scan Start mode each timeout of the +10 divisor begins a scan of channels. In all other modes the +10 rate selects the conversion rate per-channel.
ADC Rate Divisor #2, 14 of 64-bit Memory BAR[2+3] Read/Write 32-bits only
ADC Rate Divisor #2:
Write a 32-bit divisor to the ADC Rate Divisor #2 register to control the speed at which ADC Conversions occur within each scan when running in ADC
Scan Start Modes.
In “ADC Scan” start modes only, one Scan of ADC CH0 through the channel selected in +38 INx2:0 bits occurs at the rate selected at +10. During each Scan the first channel is
converted immediately, and subsequent channels are acquired at the rate selected at +14.
