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ACCES I/O Products, Inc. 

MADE IN THE USA 

PCIe-ADIO16-16F Family Manual 

 

Rev B3d 

 

ADC FIFO Data, 30 of 32-bit Memory BAR[1]Read-Only 32-bits only 

bit  D31  

D30 

D29  D28  D27  D26  D25  D24  D23  D22 through D20  D19  D18 through D16  D15 through D0 

Name  INVALID=1  RUNNING  UNUSED 

  0 (“VALID”)  RSV 

DIO1  DIO0  RSV  RSV  TEMP  MUX  SEQ  Channel2:0 

Diff  Gain2:0 

ADC Counts (Two’s complement) 

 

ADC FIFO Data:   Read the RAW-format ADC Conversion results (in twos-complement 16-bit form) and the associated status word. 
INVALID:  

If INVALID is SET then all other bits are undefined, and the entry should be discarded.  This can occur if you read from the ADC FIFO while the ADC FIFO Count 
(+28) is zero. 

RUNNING: 

SET indicates the ADC Sequencer is operating, taking either periodic (timer-driven) conversions or via the external ADC Start secondary digital function. 

DIO1:0: 

These bits indicate the state of the corresponding digital I/O pin at the time the paired ADC Conversion was sampled. 

TEMP: 

If TEMP is SET the ADC Counts are acquired from the ADAS3022’s onboard temperature sensor rather than from an analog input channel.  Refer to ADC Control 
(+38) for more information about acquiring the temperature data. 

MUX:  

If MUX is SET the ADC Counts are acquired from the ADAS3022’s Auxiliary Mux inputs rather than from the normal Analog Input Channels.  Note, the PCIe-
ADIO16-16F does not have anything usefully connected to the Aux Mux inputs and you should not bother acquiring data from them. 

SEQ: 

The SEQ bit indicates which ADC the data is from, and can be thought of as Channel:3.  That is, if SEQ is set add +8 to the channel reported by the Channel2:0 
bits. 

Channel2:0: 

The 3 Channel bits indicate from which Analog Input the paired ADC Counts were sampled.  Refer to ADC Control (+38) for important information about the 
Channel bits re Differential operation. 

Diff: 

SET indicates the paired ADC Counts were sampled in Differential mode.  Refer to ADC Control (+38) for important information about the Channel bits re 
Differential operation. 

Gain2:0: 

The 3 Gain bits indicate at what gain code the paired ADC Counts were sampled.  Refer to the gain code table in ADC Advanced Sequencer Gain Control (+18) 
for how to interpret the Gain bits. 

ADC Counts: 

16-bit two’s complement ADC counts, the ADC conversion result from the samples Channel at the specified Gain, sampled in Differential or Singled-ended / 
Pseudo-Differential mode as indicated by the Diff bit (D19). 

Please refer to the “Software Tips” section for details on how to translate RAW-format ADC data into Volts — or skip the hassle and use our AIOAIO.dll API Library: 
 

ADC_GetImmediateV(iBoard, pVolts, iChannel, iRange);,  ADC_GetImmediateScanV(iBoard, pVolts[]); etc. 

 

ADC Control, 38 of 32-bit Memory BAR[1]Read/Write 32-bits only 

bit  D31 through D19 

D18 

D17 

D16  D15  D14 through D12 

D11 

D10  D9 through D7  D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name  UNUSED 

SCAN 

CONFIG 

GO 

RSV  IN

x

2:0 

COM  RSV  Gain2:0 

/MUX  SEQ1  SEQ0  /TEMP  RSV  CMS  RSV 

Controls ADAS #0, channels 0-7 
The ADAS3022 is a very flexible ADC module and we highly recommend you use the AIOAIO.dll-provided API to avoid needing to know the following information. 

SCAN:   If SCAN is set (to 1) 

AND

 INx2:0 is non-zero then each “ADC Start” event will acquire channels 0 through INx2:0 at the rate specified in +14. 

CONFIG: If CONFIG is set then the ADC control bits (D15 through D0 of this register) will be written to the ADAS3022 
GO: 

If GO is set then, if +10 is non-zero the card will begin taking ADC conversions or scans at the rate set via +10; if +10 is zero then a single ADC conversion or scan will be 
taken. 

INx2:0:  INx specifies the individual channel to convert (in non-sequenced modes) or the last channel of the 0-INx sequence to be converted. 

Summary of Contents for PCIe-ADI12-16

Page 1: ...Sio com 10623 Roselle Street 800 326 1649 http accesio com PCIe ADIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 16 DIGITAL I O FOR PCI EXPRESS...

Page 2: ...A D Scan Start mode optimizes inter channel timing High impedance 8 channel input 1 M 32k FIFO plus DMA for efficient robust data streaming 16 Digital I O pins with flexible secondary functions Four 1...

Page 3: ...0 Ch 0 1 35 ADC IN 1 Ch 0 ADAS3022 1 ADC IN 2 Ch 1 3 37 ADC IN 3 Ch 1 ADC IN 4 Ch 2 5 39 ADC IN 5 Ch 2 ADC IN 6 Ch 3 7 41 ADC IN 7 Ch 3 ADC IN 8 Ch 4 9 43 ADC IN 9 Ch 4 ADC IN 10 Ch 5 11 45 ADC IN 11...

Page 4: ...CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquir...

Page 5: ...ol bit and status 4 W DAC Control DAC LTC2664 Command Register bits 8 W DAC Waveform Divisor DAC Waveform Points second divisor Base Clock DAC Waveform Rate this register C R ADC Base Clock Frequency...

Page 6: ...to their power on reset state see each ADC Register for more details RST BOARD Writing a 1 will reset the entire device to its power on reset state All RST bits are command bits a 1 causes the reset t...

Page 7: ...llion 125MHz but for broadest compatibility software should always read this register during init and always use the read value when calculating what if any divisor to write to the ADC Rate Divisor re...

Page 8: ...19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 15 GAIN2 0 RSV AIN 14 GAIN2 0 RSV AIN 13 GAIN2 0 RSV AIN 12 GAIN2 0 RSV AIN 11 GAIN2 0 RSV AIN 10 GAIN2 0 RSV AIN 9 GA...

Page 9: ...rol 38 for important information about the Channel bits re Differential operation Diff SET indicates the paired ADC Counts were sampled in Differential mode Refer to ADC Control 38 for important infor...

Page 10: ...5 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WDG UNUSED EXT1 EXT0 LDAC FOF FAF DTO DDONE ADCSTART ADCTRIG UNUSED enEXT1 enEXT0 enLDAC enFOF enFAF enDTO enDDONE enADCSTART enADCTRIG Read IRQ Status to determin...

Page 11: ...as a configurable active edge rising or falling SET the corresponding edgeXXX bit to select rising edge CLEAR the bit for falling edge IOGx SET each IOGx bit to configure the digital I O bits in the a...

Page 12: ...ave introduced a new source of latency the kernel userland division Application code runs in userland which must transition to the kernel in order to perform any hardware operation This transition add...

Page 13: ...all applicable EM interference and emission standards However as they are intended for use installed on motherboards and inside the chassis of industrial PCs important care in the selection of PC and...

Page 14: ...and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with equipmen...

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