Manual PCI-WDG-CSM
5
Chapter 1: Introduction
This multifunction card contains a watchdog timer. Additionally, one or more options may be included on
your card. These are: a computer power supply monitor, a computer internal temperature monitor,
capability to read the temperature, pair of opto-isolated inputs and outputs, a fan-speed control, and an
on-card alarm to signal watchdog timeout.
Watchdog
Your application program must communicate with the watchdog circuit at prescribed intervals. If this
communication ("prompt") is missed, the Watchdog can be programmed to initiate a computer reset
(reboot). If the reboot is successful, operation may be returned to the previous application program. If the
failure was temporary, proper operation is resumed. If, however, the failure is persistent, the Watchdog
will continuously reset the computer. The more frequently the Watchdog is prompted (and shorter
Watchdog time selected), the less time a faulty computer has to cause damage.
The method used by the card to detect loss of computer function is as follows:
A type 82C54 counter/timer is used. This chip contains three 16-bit counters. A number greater than zero
is set into the chip's Counters by your application program. The Watchdog is armed by software
command and the counters begin counting down. As long as the computer is operating properly, the
counters will be periodically reloaded to their original programmed values by your application program
before the counters have counted down to zero. (See Chapter 5, Programming, Foreground Watchdog
Mode, or Background Watchdog Mode for detailed information.)
If your software fails to reload the counters, then both counters continue counting until zero is reached
(timeout). When the counters 0 and 1 reach zero, the reset or power-good line is held low performing a
hardware reset through a relay contact, open collector transistor, or a de-bounced opto-isolated switch
while the optional on-board buzzer alarm sounds (if enabled). When a reset condition occurs, the reset
circuit is active until a reset pulse returns from the system bus or power is cycled to the system, or
counter 2 times out.
The clock frequency to Counter 0 is derived from the computer's clock and is
33 MHZ÷16= 2.08333 MHz. (The period is 0.48
μ
sec.)
The output of Counter 0 is used as a clock to Counter 1. Each counter can divide by any whole number
from 2 to 65,536 (2
16
), so the watchdog timeout period may vary from about 2 microseconds to 2060
seconds.
The duration of the watchdog reset output (WDRST) and ("not WDRST") can be programmed at Counter
2. There are two clock rates available for the counter and you can select the rate that best suits your
needs. The default clock rate is half the PCI bus clock speed, 16.67 MHz. You can select a lower rate
(2.08333 MHz) by a write to base C. That selection will be held until a read to base aC.
The watchdog card can generate an interrupt request one Counter 0 period-width before the reset
timeout. For example, if a reset period of 60 seconds is used with a 5 millisecond delay stored in Counter
0 (the result of a maximum value delay), an interrupt would occur at 59.995 seconds. This gives the
Interrupt handler software 5 milliseconds to refresh the watchdog before a reset action occurs. This
should allow your software to take corrective actions if the system software continued to run but the
software that should have reset the watchdog had failed. Discussion of these Watchdog Programming
Options is given in a later chapter.
