INDUSTRIAL I/O PACK SERIES APC8640 PCI BUS CARRIER BOARD
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PCI Configuration Address Space
When the computer is first powered-up, the computer’s
system configuration software scans the PCI bus to determine
what PCI devices are present. The software also determines the
configuration requirements of the PCI card.
The system software accesses the configuration registers to
determine how many blocks of memory space the carrier
requires. It then programs the carrier’s configuration registers
with the unique memory address range assigned.
The configuration registers are also used to indicate that the
PCI carrier requires an interrupt request line. The system
software then programs the configuration registers with the
interrupt request line assigned to the PCI carrier.
Since this PCI carrier is portable and not hardwired in
address space, this carrier’s device drive provided by Acromag
uses the mapping information stored in the carrier’s Configuration
Space registers to determine where the carrier is mapped in
memory space and which interrupt line will be used.
Configuration Transactions
The PCI bus is designed to recognize certain I/O accesses
initiated by the host processor as a configuration access.
Configuration uses two 32-bit I/O ports located at addresses
0CF8 and 0CFC hex. These two ports are:
•
32-bit configuration address port, occupying I/O addresses
0CF8 through 0CFB hex.
•
32-bit configuration data port, occupying I/O addresses
0CFC through 0CFF hex.
Configuration space, shown in Table 3.1, is accessed by
writing a 32-bit long-word into the configuration address port that
specifies the PCI bus, the carrier board on the bus, and the
configuration register on the carrier being accessed. A read or
write to the configuration data port will then cause the
configuration address value to be translated to the requested
configuration cycle on the PCI bus. Accesses to the
configuration data port determine the size of the access to the
configuration register addressed and can be an 8, 16, or 32-bit
operation.
Any access to the Configuration address port that is not a 32-
bit access is treated like a normal computer I/O access. Thus,
computer I/O devices using 8 or 16-bit registers are not affected
because they will be accessed as expected.
Configuration Registers
The PCI specification requires software driven initialization and
configuration via the Configuration Address space. This PCI
carrier provides 256 bytes of configuration registers for this
purpose. The PCI carrier contains the configuration registers,
shown in Table 3.2, to facilitate Plug-and-Play compatibility.
The Configuration Registers are accessed via the
Configuration Address and Data Ports. The most important
Configuration Registers are the Base Address Registers and the
Interrupt Line Register, which must be read to determine the base
address, assigned to the carrier and the interrupt request line that
goes active on a carrier interrupt request.
Table 3.1: Configuration Address Port
BIT FUNCTION
31
Enables accesses to Configuration Data to be
translated to configuration cycles on the PCI bus.
30-24
Reserved, Return 0 when read.
23-16 Bus
Number
Choose a specific PCI bus in the system. Zero
if only one PCI bus.
15-11 Device
Number
Choose a specific device/PCI board on the
bus.
10-8 Function
Number
Choose a specific function in a device.
Function number is zero for the APC8640
7-2 Register
Number
Used to indicate which PCI Configuration
Register to access. The Configuration
Registers and their corresponding register
numbers are given in Table 3.2.
1-0
Read Only bits that return 0.
Table 3.2: Configuration Registers
Reg.
Num.
D31
D24
D23
D16
D15
D8
D7
D0
0
Device ID=1024
Vendor ID= 10B5
1
Status Command
2
Class Code
Rev ID
3
BIST Header
Latency Cache
4
Base Addr. Memory Mapped Configuration Registers
5
Base Address for I/O Mapped Configuration Registers
6
PCIBar2:
Base Address for Carrier/IO/ID/INT Space
7
PCIBar3:
Base Address for Memory Space
1
8:10
Not Used
11
Subsystem ID
Subsystem Vendor ID
12
Not Used
13
Reserved
14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
1. Optional address space that is enabled/disabled via a jumper
prior to power-up.
MEMORY MAP
This board consumes a 1K byte block and an optional 64M
byte block that is enabled via configuration jumper prior to power-
up. The 1K byte block of memory consumed by the board is
composed of blocks of memory for the ID, I/O and INT spaces
corresponding to five IP modules. In addition, a small portion of
the 1K byte address space contains registers specific to the
function of the carrier board. The 64M byte block of memory is
composed of the Memory Space for up to five IP modules.
The carrier is configured to map this 1K byte and 64M byte
block of memory into 32-bit memory space. The system
configuration software will allocate space by writing the assigned
addresses into the corresponding Base Address registers of the
Configuration Registers. The memory map for APC8640 is
shown in Tables 3.3.
