ADM-VPX3-9V2 User Manual
3.9 USB Interface
The USB connector on the debug board is used to directly access the system monitor. All voltages, currents,
temperatures, and non-volatile clock configuration settings can be accessed using Alpha Data's avr2util software
at this interface.
Avr2util for Windows and the associated USB driver is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util for Linux is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/linux/
Use "avr2util.exe /?" to see all options.
For example "avr2util.exe /usbcom com4 display-sensors" will display all sensor values.
For example "avr2util.exe /usbcom com4 setclknv 1 100000000" will set the PROGCLK_1 to 100MHz. setclk
index 0 = PROGCLK_0, index 1 = PROGCLK_1, index 2 = REFCLK300 (DRAM), index 3 = FABRIC_CLK.
Change 'com4' to match the com port number assigned under windows device manager.
3.10 Configuration
There are two main ways of configuring the FPGA on the ADM-VPX3-9V2:
•
From Flash memory, at power-on, as described in
•
Using JTAG at either the debug board or P0
3.10.1 Configuration From Flash Memory
The FPGA can be automatically configured at power-on from one 2 Gbit QSPI flash memory device configured
as an x4 SPI device (Micron part numbers MT25QU02GCBB8E12-0). These flash devices are typically divided
into two regions of 128 MiByte each, where each region is sufficiently large to hold an uncompressed bitstream
for a VU9P or VU13P FPGA.
The ADM-VPX3-9V2 is shipped with a simple PCIe endpoint bitstream which should be visible to the operating
system (using e.g. Windows Device Manager or “lspci” in Linux) in order to provided confidence that the card is
working correctly when installed in a system. On request, Alpha Data can pre-load custom bitstreams during
production test. Please contact sales@alpha-data.com in order to discuss this possibility.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and
the Fallback MultiBoot are discussed in detail in Xilinx UG570.
At power-on, the FPGA attempts to configure itself automatically in SPI master mode, depending on the header
of the bitstream that has been flashed into the card. This normally results in SPIx4 configuration at EMCCLK
frequency. The configuration scheme used in the ADM-VPX3-9V2 is compatible with Multiboot; see Xilinx UG570
for details. The FPGA can also be made to reconfigure itself from an arbitrary Flash address using the ICAPE3
primitive; this is also described in Xilinx UG570.
The image loaded can also support tandem PROM or tandem PCIE with field update configuration methods.
These options reduce power-on load times to help meet the PCIe reset timing requirements. Tandem with field
also enables a host system to reconfigure the user FPGA logic without losing the PCIe link, a useful feature
when system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA.
This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system
monitor can be accessed with avr2util over USB at the front panel and rear edge.
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Functional Description
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