3
During command execution, additional user input may be required depending on the command function.
For commands that accept an optional <width> to modify the memory access size, the valid values are:
.B
8-bit (byte) access
.W
16-bit (word) access
.L
32-bit (long) access
When no <width> option is provided, the default width is .W, 16-bit.
The core ColdFire register set is maintained by dBUG. These are listed below:
A0-A7
D0-D7
PC
SR
All control registers on ColdFire are not readable by the supervisor programming model, and thus not
accessible via dBUG. User code may change these registers, but caution must be exercised as changes may
render dBUG useless.
A reference to “SP” actually refers to “A7”.
2.2 OPERATIONAL PROCEDURE
System power-up and initial operation are described in detail in Chapter 1. This information is repeated
here for convenience and to prevent possible damage.
2.2.1 System Power-up
a.
Be sure the power supply is connected properly prior to power-up.
b. Make sure the terminal is connected to TERMINAL (J1) connector.
c.
Turn power on to the board.
2.2.2 System Initialization
The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked.
dBUG performs the following configurations of internal resources during the initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash. However, a copy
of the exception table is made at address $00000000 in SRAM. To take over an exception vector, the user
places the address of the exception handler in the appropriate vector in the vector table located at
0x00000000, and then points the VBR to 0x00000000.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are placed in a stop
condition. Interrupt controller registers initialized with unique interrupt level/priority pairs. The Port A
general purpose I/O pins are configured for dedicated peripheral functions, i.e. the UART.
