3
On SBC5204, the internal Timers, Software Watchdog Timer, and UART are disabled and not used.
However, the software watchdog is programmed for Level 7, priority 2 and uninitialized vector. The
UART is programmed for Level 3, priority 2 and autovector. The Timers are at Level 5 with Timer 1 with
priority 3 and Timer 2 with priority 2 and both for autovector.
The SBC5204 uses -IRQ0 to support the ABORT function using the ABORT switch S1 (black switch).
This switch is used to force a non-maskable interrupt (level 7, priority 3) if the user's program execution
should be aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Since
the ABORT switch is not capable of generating a vector in response to level seven interrupt acknowledge
from the processor, the debugger programs this request for autovector mode.
The MC68HC901 reports its interrupt request on -IRQ1 line which is set for Level 1, priority 3. It uses
the vectored mode for acknowledgment. The chip-select -CS3 is used to generate the -IACK signal for
MC68HC901. The MC68HC901 is programmed to generate vectors $F0 to $FF. This should not be
changed.
The -IRQ2 and -IRQ3 lines of the MCF5204 are not used on this board. However, the -IRQ2 is
programmed for Level 1 with priority 1 and the -IRQ3 is programmed for Level 1 with priority 2. The user
may use these lines for external interrupt request. Refer to MCF5204 User’s Manual for more information
about the interrupt controller.
3.1.6 Internal SRAM
The MCF5204 has 512 bytes of internal memory. This memory is mapped to $02000000 and is not used
by the dBUG. It is available to the user.
3.1.7 The MCF5204 Registers and Memory Map
The memory and I/O resources of the SBC5204 are divided into three groups, MCF5204 Internal, External
resources, and the ISA Bus address. All the I/O registers are memory mapped.
The MCF5204 has built in logic and six Chip-select pins (-CS0, -CS1, -CS2, -CS3, -CS4, -CS5) which
are used to enable external memory and I/O devices. There are eighteen (18) 32-bit registers to specify the
address range, type of access, and the method of DTACK generation for each chip-select pin. These
registers are programmed by dBUG to map the external memory and I/O devices.
The SBC5204 uses chip-select zero (-CS0) to enable the EPROM/Flash ROM ( refer to Section 3.3.) The
SBC5204 also uses -CS1 to enable the SRAM (refer to Section 3.2), -CS2 for enabling the MC68HC901,
-CS3 for Interrupt acknowledge of MC68HC901, and -CS4 for ISA Bus I/O space. The SBC5204 does
not use the -CS5.
The chip select mechanism of the MCF5204 allows the memory mapping to be defined based on the
memory space desired (User/Supervisor, Program/Data spaces).
All the MCF5204 internal registers, configuration registers, parallel I/O port registers, DUART registers
and system control registers are mapped by MBAR register at 1K-byte boundary. It is mapped to
$01000000 by dBUG. For complete map of these registers refer to the MCF5204 User's Manual.
The SBC5204 board can have up to 1M bytes of SRAM installed. The first 1M bytes are reserved for this
memory. Refer to Section 3.2 for a discussion of RAM. The dBUG is programmed in two 29F010 Flash
