MCOR Control Register
Bit
[1]
MCOR Inhibit
‘1’
MCOR Inhibit Asserted
‘0’
MCOR Inhibit Not Asserted
[0]
MCOR Reset
‘1’
MCOR Reset Asserted
‘0’
MCOR Reset Not Asserted
MCOR Set Control/Reset Control Registers
Bit
[1]
MCOR Inhibit
[0]
MCOR Reset
Interlock and Magnet Fault Registers
(note that 4 Interlock outputs and 8 Magnet Fault inputs are
not currently implemented)
Offset
Base = 0x0500
0x00
External Interlocks Status
0x04
Set External Interlocks
UInt32
0x08
Reset External Interlocks
0x0C
Magnet Fault Status
0x10
Magnet Latched Fault Status
0x14
Reset Magnet
Latched Fault Status
External Interlock Status
Bit
[31:04]
Unused
[03:00]
Output
External Interlock Set/Reset Output (0x0004,0x0008)
Bit
[31:04]
Unused
[03:00]
Output
Input Status
Bit
[31:09]
8
Water Fault
[07:00]
Inputs
Input Status (0x000C)
Bit
[31:09]
8
Water Fault (Turn off Bulk)
[07:00]
Inputs