M
ODEL
SL900A V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2006.06.30
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
21/51
SL900A
T
ECHNICAL
M
ANUAL
Figure 14. UART block diagram
.
RX data Timeout Interrupt :
When virtual FIFO mode is disabled, RX data Timeout Interrupt is generated if all of the following apply :
1.
FIFO contains at least on character.
2.
The most recent character was received longer than four character periods ago(including all start, parity
and stop bit)
3.
The most recent CPU read of the FIFO was longer than four character periods ago.
When virtual FIFO mode is enabled, RX Data timeout Interrupt is generated if all of the following apply:
1.
FIFO is empty.
2.
The most recent character was received longer than four character periods ago(including all start, parity
and stop bit)
3.
The most recent CPU read of the FIFO was longer than four character periods ago
4.7
IrDA framer
IrDA
framer,
which is depicted in Figure 15, is implemented to reduce the CPU loading for IrDA transmission.
IrDA framer functional block can be divided into two parts : the transmitting part and the receiving part. In the
transmitter, it will perform BOFs addition, byte stuffing, the addition of 16bits FCS and EOF appendence. In the
receiving part, it will execute BOFs removal, ESC character removal, CRC checking and EOF detection. In
addition, the framer will perform 3/16 modulation and demodulation to connect to the IR transceiver. The
transmitter and receiver all need DMA channel.
Figure 15. IrDA Block Diagram.
Summary of Contents for SL900A
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