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Addendum List for Revision 7.1

MPC5607B Reference Manual Errata, Rev. 1

Freescale Semiconductor 

3

Chapter 16, Enhanced Direct 

Memory Access (eDMA), 
page 330

Replace 

Section 16.5.8, Dynamic programming,

 with the following:

16.5.8

Dynamic programming

16.5.8.1

Dynamic channel linking

Dynamic channel linking is the process of setting the TCD.major.e_link bit 
during channel execution. This bit is read from the TCD local memory at the 
end of channel execution, thus allowing the user to enable the feature during 
channel execution. 

Because the user is allowed to change the configuration during execution, a 
coherency model is needed. Consider the scenario where the user attempts to 
execute a dynamic channel link by enabling the TCD.major.e_link bit at the 
same time the eDMA engine is retiring the channel. The TCD.major.e_link 
would be set in the programmer’s model, but it would be unclear whether the 
actual link was made before the channel retired.

The coherency model in 

Table 16-24

 is recommended when executing a 

dynamic channel link request. 

 

For this request, the TCD local memory controller forces the TCD.major.e_link 
bit to zero on any writes to a channel’s TCD.word7 after that channel’s 
TCD.done bit is set, indicating the major loop is complete. 

NOTE

The user must clear the TCD.done bit before 
writing the TCD.major.e_link bit. The TCD.done 
bit is cleared automatically by the eDMA engine 
after a channel begins execution.

Table 1. MPC5607BRM Rev 7.1 Addenda (continued)

Location

Description

Table 16-24. Coherency model for a dynamic channel link request 

Step

Action

1

Write 1b to the TCD.major.e_link bit.

2

Read back the TCD.major.e_link bit.

3

Test the TCD.major.e_link request status:
 • If TCD.major.e_link = 1b, the dynamic link attempt was successful.
 • If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel 

was already retiring).

Summary of Contents for MPC5607B

Page 1: ...ference Manual order number MPC5607BRM For convenience the addenda items are grouped by revision Please check our website at http www freescale com powerarchitecture for the latest updates The current...

Page 2: ...he MMU Chapter 6 Clock Description page 132 Add Note to Section 6 8 4 1 Crystal clock monitor Note Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is greater than FIRC 2RCD...

Page 3: ...be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The coherency model in Table 16 24 is recommended when executing a dynamic channel...

Page 4: ...model are shown in the following subsections Method 1 has the advantage of reading the major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather reque...

Page 5: ...unique TCD ID in the TCD major linkch field for each TCD associated with a channel using dynamic scatter gather 2 Write 1b to theTCD d_req bit Note Should a dynamic scatter gather attempt fail setting...

Page 6: ...ttempt fail setting the d_req bit will prevent a future hardware activation of this channel This stops the channel from executing with a destination address daddr that was calculated using a scatter g...

Page 7: ...the latest message is always available to the application If the buffer lock function is enabled LINCR1 RBLM 0 the most recent message is discarded and the previous message is available in the buffer...

Page 8: ...Clocking Scheme to read This clock selection feature may not be available in all MCUs A particular MCU may not have a PLL in which case it would have only the oscillator clock or it may use only the...

Page 9: ...ompletion if the ADC is shut down while performing a CTU triggered conversion the CTU is not notified and will not be able to trigger further conversions until the device is reset Chapter 30 Flash Mem...

Page 10: ...e manual addendum document Chapter 32 Register Protection page 954 In Table 32 5 Protected registers change the module base address for the CMU_CSR register from C3FE00E0 to C3FE0000 Table 2 Revision...

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