background image

Addendum List for Revision 7.1

MPC5607B Reference Manual Errata, Rev. 1

Freescale Semiconductor 

5

Chapter 16, Enhanced Direct 

Memory Access (eDMA), 
page 330 (cont.)

16.5.8.2.2

Method 2 (channel using major loop linking)

For a channel using major loop channel linking, the coherency model in 

Table 16-26

 may be used for a dynamic scatter/gather request. This method 

uses the TCD.dlast_sga field as a TCD identification (ID). 

For a channel using major loop channel linking, the coherency model in 

Table 16-26

 may be used for a dynamic scatter/gather request. This method 

uses the TCD.dlast_sga field as a TCD identification (ID). 

Table 1. MPC5607BRM Rev 7.1 Addenda (continued)

Location

Description

Table 16-25. Coherency model for method 1

Step

Action

1

When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for 
each TCD associated with a channel using dynamic scatter/gather.

2

Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a 

future hardware activation of this channel. This stops the channel from 
executing with a destination address (daddr) that was calculated using a 
scatter/gather address (written in the next step) instead of a dlast final offset 
value.

3

Write theTCD.dlast_sga field with the scatter/gather address.

4

Write 1b to the TCD.e_sg bit.

5

Read back the 16 bit TCD control/status field.

6

Test the TCD.e_sg request status and TCD.major.linkch value:
 • If e_sg = 1b, the dynamic link attempt was successful.
 • If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link 

did not succeed (the channel was already retiring).

 • If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was 

successful (the new TCD’s e_sg value cleared the e_sg bit).

Summary of Contents for MPC5607B

Page 1: ...ference Manual order number MPC5607BRM For convenience the addenda items are grouped by revision Please check our website at http www freescale com powerarchitecture for the latest updates The current...

Page 2: ...he MMU Chapter 6 Clock Description page 132 Add Note to Section 6 8 4 1 Crystal clock monitor Note Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is greater than FIRC 2RCD...

Page 3: ...be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The coherency model in Table 16 24 is recommended when executing a dynamic channel...

Page 4: ...model are shown in the following subsections Method 1 has the advantage of reading the major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather reque...

Page 5: ...unique TCD ID in the TCD major linkch field for each TCD associated with a channel using dynamic scatter gather 2 Write 1b to theTCD d_req bit Note Should a dynamic scatter gather attempt fail setting...

Page 6: ...ttempt fail setting the d_req bit will prevent a future hardware activation of this channel This stops the channel from executing with a destination address daddr that was calculated using a scatter g...

Page 7: ...the latest message is always available to the application If the buffer lock function is enabled LINCR1 RBLM 0 the most recent message is discarded and the previous message is available in the buffer...

Page 8: ...Clocking Scheme to read This clock selection feature may not be available in all MCUs A particular MCU may not have a PLL in which case it would have only the oscillator clock or it may use only the...

Page 9: ...ompletion if the ADC is shut down while performing a CTU triggered conversion the CTU is not notified and will not be able to trigger further conversions until the device is reset Chapter 30 Flash Mem...

Page 10: ...e manual addendum document Chapter 32 Register Protection page 954 In Table 32 5 Protected registers change the module base address for the CMU_CSR register from C3FE00E0 to C3FE0000 Table 2 Revision...

Reviews: