CPU to PCI Write Buffer
This controls the CPU write buffer to the PCI bus. If this buffer is disabled, the
CPU writes directly to the PCI bus. Although this may seem like the faster and
thus, the better method, this isn't true. Because the CPU bus is faster than the
PCI bus, any CPU writes to the PCI bus has to wait until the PCI bus is ready
to receive data. This prevents the CPU from doing anything else until it has
completed sending the data to the PCI bus. Enabling the buffer enables the
CPU to immediately write up to 4 words of data to the buffer so that it can
continue on another task without waiting for those 4 words of data to reach
the PCI bus. The data in the write buffer will be written to the PCI bus when
the next PCI bus read cycle starts. The difference here is that it does so
without stalling the CPU for the entire CPU to PCI transaction. Therefore,
it's recommended that you enable the CPU to PCI write buffer.
PCI Dynamic Bursting
W hen enabled, data transfer on the PCI bus, where possible, make use of the
high-performance PCI bust protocol, in which greater amounts of data are
transferred at a single command.
PCI Master 0 WS Write
This function determines whether there's a delay before any writes to the PCI
bus. If this is enabled, then writes to the PCI bus are executed immediately
(with zero wait states), as soon as the PCI bus is ready to receive data. But if
it is disabled, then every write transaction to the PCI bus is delayed by one
wait state. Normally, it's recommended that you enable this for faster PCI
performance. However, disabling it may be useful when overclocking the PCI
bus results in instability. The delay will generally improve the overclockability of
the PCI bus.
PCI Master 0 WS Read
This function determines whether there's a delay before any writes to the PCI
bus. If this is enabled, then read to the PCI bus are executed immediately
(with zero wait states), as soon as the PCI bus is ready to receive data. But
if it is disabled, then every read transaction to the PCI bus is delayed by one
wait state. Normally, it's recommended that you enable this for faster PCI
performance. However, disabling it may be useful when overclocking the PCI
bus results in instability. The delay will generally improve the overclockability
of the PCI bus.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specifica-
tion version 2.1.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specifica-
tion version 2.1.
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3312400 User's Manual
