Manual Number: 40110-005-2
Page 87
Code
Description
E6
Enabling floppy drive controller and timer IRQ’s. Enabling internal cache memory.
ED
Initializing floppy drive.
EE
Looking for floppy diskette in drive A:. Reading first sector of diskette.
EF
Read error occurred while reading floppy drive in drive A:.
F0
Searching for AMIBOOT.ROM file in root directory.
F1
AMIBOOT.ROM file not in root directory.
F2
Reading and analyzing floppy diskette FAT to find clusters occupied by
AMIBOOT.ROM file.
F3
Reading AMIBOOT.ROM file next, cluster by cluster.
F4
AMIBOOT.ROM file not correct size.
F5
Disabling internal cache memory next.
FB
Detecting type of flash ROM next.
FC
Erasing flash ROM next.
FD
Programming flash ROM next.
FF
Flash ROM programming successful. Restarting system BIOS next.
Runtime code is uncompressed in F000 shadow RAM.
03
NMI is disabled. Checking for soft reset/power-on next.
05
BIOS stack has been built. Disabling cache memory next.
06
Uncompressing POST code next.
07
Initializing CPU and CPU data area next.
08
CMOS checksum calculation to be done next.
0A
CMOS checksum calculation done. Initializing CMOS status register for date and
time next.
0B
CMOS status register initialized. Next, performing any required initialization
before keyboard BAT command issued.
0C
Keyboard controller input buffer free. Issuing BAT command to keyboard controller
next.
0E
Keyboard controller BAT command result verified. Performing any necessary
initialization after keyboard controller BAT test next.
0F
Initialization after keyboard controller BAT command test done. Keyboard
command byte to be written next.
10
Keyboard controller command byte is written. Issuing Pin 23,24 blocking/unblocking
command next.
11
Checking if <End> or <Ins> keys were pressed during power-on next. Initializing
CMOS RAM if the “Initialize CMOS RAM in every boot” AMIBIOS POST option
was set in AMIBCP or the <End> key was pressed.
12
Disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2 next.
13
Video display disabled and port B initialized. Initializing chipset next.
14
8254 timer test to begin next.
19
8254 timer test over. Starting memory refresh test next.
1A
Memory refresh line is toggling. Checking 15 microsecond on/off time next
Summary of Contents for SB686P Series
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Page 14: ...Manual Number 40110 005 2 Page 4...
Page 27: ...Manual Number 40110 005 2 Page 17 ISA Bus Pin Numbering...
Page 37: ...Manual Number 40110 005 2 Page 27 PCI Local Bus Pin Numbering...
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