Manual Number: 40110-005-2
Page 89
Code
Description
48
Patterns written in base memory. Determining amount of memory below 1MB
memory next.
49
Amount of memory below 1MB found and verified. Determining amount of
memory above 1MB memory next.
4B
Amount of memory above 1MB found and verified. Checking for soft reset and
clearing memory below 1MB for soft reset next. (If power-on situation, going to
checkpoint 4EH next.)
4C
Memory below 1MB has been cleared via soft reset. Clearing memory above 1MB
next.
4D
Memory above 1MB has been cleared via soft reset. Saving memory size next.
(Going to checkpoint 52H next.)
4E
Memory test started, but not as result of soft reset. Displaying first 64KB memory
size next.
4F
Memory size display started. Display is updated during memory test. Performing
sequential and random memory tests next.
50
Memory below 1MB has been tested and initialized. Adjusting displayed memory
size for relocation and shadowing next.
51
Memory size display adjusted for relocation and shadowing. Testing memory
above 1MB next.
52
Memory above 1MB has been tested and initialized. Saving memory size information
next.
53
Memory size information and CPU registers are saved. Entering real mode next.
54
Shutdown was successful. CPU in real mode. Disabling Gate A20 line, parity and
NMI next.
57
A20 address line, parity and NMI are disabled. Adjusting memory size depending
on relocation and shadowing next.
58
Memory size adjusted for relocation and shadowing. Clearing “Hit <DEL>”
message next.
59
“Hit <DEL>” message cleared. “Wait...” Message displayed. Starting DMA and
interrupt controller tests next.
60
DMA page register test passed. Performing DMA controller 1 base register test
next.
62
DMA controller1 base register test passed. Performing DMA controller 2 base
register test next.
65
DMA controller_2 base register test passed. Programming DMA controllers 1 and
2 next.
66
Completed programming DMA controllers 1 and 2. Initializing 8259 interrupt
controller next.
67
Completed 8259 interrupt controller initialization.
7F
Extended NMI sources enabling in progress.
80
Keyboard test started. Clearing output buffer, checking for stuck keys. Issuing
keyboard reset command next.
81
Keyboard reset error or stuck key found. Issuing keyboard controller interface test
command next.
Summary of Contents for SB686P Series
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Page 14: ...Manual Number 40110 005 2 Page 4...
Page 27: ...Manual Number 40110 005 2 Page 17 ISA Bus Pin Numbering...
Page 37: ...Manual Number 40110 005 2 Page 27 PCI Local Bus Pin Numbering...
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