INSTRUCTION TIMING
A - 296
INSTRUCTION SET DETAILS
MOTOROLA
cycles that may be required over and above those needed for the basic MACR instruc-
tion due to the parallel move portion of the instruction.
2. Evaluate the “mv’’ term using Table A-7.
The parallel move portion of the MACR instruction consists of an XY memory move.
According to Table A-7, the parallel move portion of the instruction will require mv=0
additional instruction program words and mv=(ea+axy) additional oscillator clock cycles.
The term “ea” represents the number of additional (if any) oscillator clock cycles that are
required for the effective addressing move specified in the parallel move portion of the
instruction. The term “axy” represents the number of additional (if any) oscillator clock
cycles that are required to access an
XY
memory operand.
3. Evaluate the “ea’’ term using Table A-13.
The parallel move portion of the MACR instruction consists of an XY memory move
which uses both address register banks (R0–R3 and R4–R7) in generating the effective
addresses of the XY memory operands. Thus, the two effective address operations
occur in parallel, and the larger of the two “ea’’ terms should be used. The X memory
move operation uses the “postdecrement by 1” effective addressing mode. According to
Table A-13, this operation will require ea=0 additional oscillator clock cycles. The Y
memory move operation uses the “postincrement by 1” effective addressing mode.
According to Table A-13, this operation will also require ea=0 additional oscillator clock
cycles. Thus, using the maximum value of “ea’’, the effective addressing modes used in
the parallel move portion of the MACR instruction will require ea=0 additional oscillator
clock cycles.
4. Evaluate the “axy’’ term using Table A-14.
The parallel move portion of the MACR instruction consists of an XY memory move.
According to Table A-14, the term “axy’’ depends upon where the referenced X and Y
memory locations are located in the DSP56K memory space.
External
memory
accesses require additional oscillator clock cycles according to the number of wait states
programmed into the DSP56K bus control register (BCR). Thus, assuming that the 16-bit
bus control register contains the value $1135, external
X
memory accesses require wx=1
w
ait state of additional oscillator clock cycle while external
Y
memory accesses require
wy=1
w
ait state or additional oscillator clock cycle. For this example, the X memory refer-
ence is assumed to be an
internal
reference; the Y memory reference is assumed to be
an
external
reference. Thus, according to Table A-14, the XY memory reference in the
parallel move portion of the MACR instruction will require axy=wy=1 additional oscillator
clock cycle.
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...