PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 31 -
Revision 1.31
10 SERIAL PERIPHERAL INTERFACE (SPI) MODE
10.1 M
ICROCONTROLLER
I
NTERFACE
A four-wire (SCLK, MOSI, MISO &
SS
) SPI interface can be used for serial communication to the
ISD1700 device. The ISD1700 Series is configured to operate as a peripheral slave device. All
operations can be controlled through this SPI interface.
To allow compatibility with Standalone mode, some SPI commands: PLAY, REC, ERASE, FWD,
RESET and G_ERASE
behave similarly as the corresponding features in Standalone mode. In
addition, SET_PLAY, SET_REC and SET_ERASE commands allow the user to specify the start
and the end addresses of the operation. Besides, there are commands accessing the APC
register, which controls the configuration of the analog paths used by the device, and etc.
10.2 SPI
I
NTERFACE
O
VERVIEW
The ISD1700 series operates via the SPI serial interface with the following protocol.
Data transfer protocol requires that the microcontroller’s SPI shift registers are clocked out on the
falling edge of the SCLK. The SPI protocol of the ISD1700 device is as follows:
1. A SPI transaction is initiated on the falling edge of the
SS
pin.
2.
SS
must be held Low during the entire data transfer process.
3. Data is clocked into the device through the MOSI pin on the rising edge of the SCLK signal
and clocked out of the MISO pin on the falling edge of the SCLK signal, with LSB first.
4. The opcodes contain command, data and address bytes, depending upon the command type.
5. While control and address data are shifted into the MOSI pin, the status register and current
row address are simultaneously shifted out of the MISO pin.
6. The SPI transaction is completed by raising the
SS
to High.
7. After completing an operational SPI command, an active Low interrupt is generated. It will stay
Low until it is reset by the CLR_INT command.
10.2.1 SPI Transaction Format
Figure 10.1 describes the format of the SPI transaction. Data are shifted into the device on
the MOSI data line. Concurrently, the device status and current row address and other data
are returned to the host via the MISO data line. In order to perform functions normally,
correct numbers of data bytes are required to shift into the MOSI. Meanwhile, the related
numbers of bytes of information are shifted out from MISO.
MOSI
CMD_Byte
Data Byte 1
Data Byte 2 or
Start Address
(Low Byte)
Data Byte 3 or
Start Address
(High Byte)
End Address
(Low Byte)
End Address
(Mid Byte)
LSB
MSB
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte
End Address
(High Byte)
7th Byte
MISO
Status Register 0 (SR0)
(Low Byte & High Byte)
Data Byte 2 or
SR0 (High Byte)
Data Byte 1 or
SR0 (Low Byte)
LSB
MSB
1st Byte
2nd Byte
3rd Byte
4th Byte
SR0
(High Byte)
6th Byte
SR0
(Low Byte)
7th Byte
SR0
(Low Byte)
5th Byte
Figure 10.1 SPI Transaction Format
