PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 33 -
Revision 1.31
10.2.3 MISO Data Format
Data is clocked out of the
M
aster
I
n
S
lave
O
ut pin of ISD1700 device on the falling edge of
the SCLK signal, with LSB first. MISO returns the status generated by the last command and
current row address <A10:A0> in the first two bytes for all operations. The commands
RD_STATUS, DEVID, RD_PLAY_PNTR, RD_REC_PNTR and RD_APC provide additional
information in the subsequent bytes (see below sections for more details). The sequence of
MISO is shown in the table below.
Table 10.2 MISO Data Sequence
LSB 1
st
Byte : Status Register 0 (Low Byte) MSB
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
CMD_ Err
Memory Full
Power Up EOM Interrupt A0
A1
A2
LSB 2
nd
Byte : Status Register 0 (High Byte) MSB
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
A3 A4 A5
A6
A7
A8
A9
A10
LSB 3
rd
Byte : Data Byte 1 or SR0 (Low Byte) MSB
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
D0 /
CMD_ Err
D1/
Memory Full
D2 /
Power Up
D3 /
EOM
D4 /
Interrupt
D5 /
A0
D6 /
A1
D7 /
A2
LSB 4
th
Byte : Data Byte 2 or SR0 (High Byte) MSB
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
D8 / A3
D9 / A4
D10 / A5
D11 / A6
D12 / A7
D13 / A8
D14 / A9
D15 / A10
LSB 5
th
Byte : SR0 (Low Byte) MSB
Bit 32
Bit 33
Bit 34
Bit 35
Bit 36
Bit 37
Bit 39
Bit 39
CMD_ Err
Memory Full
Power Up EOM Interrupt A0
A1
A2
LSB 6
th
Byte : SR0 (High Byte) MSB
Bit 40
Bit 41
Bit 42
Bit 43
Bit 44
Bit 45
Bit 46
Bit 47
A3 A4 A5
A6
A7
A8
A9
A10
LSB 7
th
Byte : SR0 (Low Byte) MSB
Bit 48
Bit 49
Bit 50
Bit 51
Bit 52
Bit 53
Bit 54
Bit 55
CMD_ Err
Memory Full
Power Up EOM Interrupt A0
A1
A2
The status bits of the 1
st
byte provide important information on the result of the previous
command sent. In particular, bit 0 (command error bit) indicates whether the chip is able
to process the previous command or not. The address bits <A10:A0> represent the
address location. The contents of the Data Bytes 1 & 2 are depended upon the previous
command. The 5
th
, 6
th
and 7
th
bytes are the repeat of SR0 status.
