M5251C3 Evaluation Board Users Guide, Rev. 0
Freescale Semiconductor
3-3
•
Software watchdog timer module
•
Two general purpose timer modules
•
UART module
•
I
2
C module
•
Audio interface modules
•
DMA module
•
QSPI module
•
CAN module
•
USB module
•
ATA module
•
Flash media module
All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers.
NOTE
No interrupt sources should have the same level and priority as another.
Programming two interrupt sources with the same level and priority can
result in undefined operation.
The M5251C3 hardware uses -INT1 to support the ABORT function using the ABORT switch (S2). This
switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be aborted
without issuing a RESET command. See
Section 2.2.2.2, “ABORT Button
for more
information on ABORT.) Since the ABORT switch is not capable of generating a vector in response to a
level seven interrupt acknowledge from the processor, the dBUG programs this interrupt request for
autovector mode.
See the
MCF5251 Reference Manual
for more information about the interrupt controller.
3.1.7
Internal SRAM
The MCF5251 processor has 128 Kbtyes of internal memory which may be programmed as data or
instruction memory. This memory is mapped to 0x20000000 and configured as data space but is not used
by the dBUG monitor except during system initialization. After system initialization is complete, the
internal memory is available to the user. The memory can be relocated to any 32-Kbyte boundary.
3.1.8
MCF5251 Registers and Memory Map
The memory and I/O resources of the M5251C3 hardware are divided into two groups, MCF5251 internal
and external resources. All the I/O registers are memory mapped.
The MCF5251 processor has built in logic and up to four chip-select pins (-CS[3:0]) which are used to
enable external memory and I/O devices. In addition there are -SDRAS and -SDCAS lines available for
controlling SDRAMs. There are registers to specify the address range, type of access and the method of
Summary of Contents for freescale M5251C3
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