Sharp UP-5700 Service Manual Download

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12. Pos System Controller 2

12-1. PSC2 Feature Outline

Sharp’s LZ9A10000 is used as the PSC2, controlling the POS device
connected to the ISA bus.

BIOS ROM control

MASK ROM control

ROM and RAM disk control

The PSC2 internally expands dedicated interrupts to allow ISA inter-
rupts to be assigned.

Incorporated DOS convertible UART2 channel

Incorporated UART2 channel for VFD I/F

Incorporated UART1 channel for touch panel

Incorporated 2 channels of MCR I/F

Incorporated 4 channels of drawer I/F

Incorporated 2 channels of CKDC I/F

Incorporated mode key I/F and clerk key I/F

Supported input ports of system SW

Incorporated 2 channels of 8-bit timer counter

Decoded output of super I/O upper address

Reset control

12-2. Memory Control

12-2-1. BIOS ROM Control

Up to 512K bytes of flash ROM memory with 16-bit configuration can
be used as BIOS ROM. The interface is designed to be connected to
the ISA bus.

The PSC2 outputs address A18 signal to the BIOS ROM. So when
setting the BIOS ROM area to C0000H to FFFFFH using a chip set,
this area can be accessed in 256K bytes.

12-2-2. MASK ROM Control

Up to 8M bytes of mask ROM memory with 16-bit configuration can
be used as mask ROM. The interface is designed to be connected to
the ISA bus. The specifications of decoding is as the following table,
so MROMCS# signal is generated.

12-2-3. FLASH ROM Control

Up to 8M bytes of flash ROM memory with 16-bit configuration can be
used as flash ROM. The interface is designed to be connected to the
ISA bus.

FROS0# area:

Bank base a 000000H to 003FFFH Bank 200H to 27FH

FROS1# area:

Bank base a 000000H to 003FFFH Bank 280H to 2FFH

FROS2# area:

Bank base a 000000H to 003FFFH Bank 300H to 37FH

FROS3# area:

Bank base a 000000H to 003FFFH Bank 380H to 3FFH

12-2-4. RAM Disk Control

Up to 8M bytes of PS RAM with 16-bit configuration can be controlled
as a RAM disk. The interface is designed to be connected to the ISA
bus.

PRAS0 area:

Bank base a 004000H to 007FFFH Bank 000H to 03FH

PRAS1 area:

Bank base a 004000H to 007FFFH Bank 040H to 07FH

PRAS2 area:

Bank base a 004000H to 007FFFH Bank 080H to 0BFH

PRAS3 area:

Bank base a 004000H to 007FFFH Bank 000H to 1FFH

The refresh control of pseudo SRAM is performed as follows:

Use a refresh cycle to disable the decode output to the pseudo
SRAM during the refresh cycle, and output a refresh signal with the
speed of about 135ns from the PSC2 to OE#/RFSH# of the pseudo
SRAM. So the pseudo SRAM can be refreshed automatically without
taking the arbitration with other bus masters into consideration.

After power off (POFF#="0") is detected, if the power down of DC 5V
(PWRGOOD="0") is detected or 200ms elapsed, PWRGD signal is
automatically set to "0" by hardware. Applications must be completely
shunted before the PSC2 automatically shutdowns. When resetting
using the software, enabling the shutdown enable bit (bit 0 of special
system register 1) allows hardware reset. After enabling this bit, the
pseudo SRAM goes in self refresh cycle with synchronized with the
refresh cycle. After powering up again and REFRESH signal is out-
putted and stable, disable the shutdown enable bit. Then the pseudo
SRAM is refreshed in automatic refresh mode.

12-2-5. BIOS Bank Control

This is a register to set banks in 512K bytes of BIOS ROM. Data set
in the BBR0 is outputted from BA18.

12-2-6. Bank Base Address Control

This is a register to set the base address of ROM and RAM disk
bank.

12-2-7. Mask/Flash ROM Bank Control

This is a register to set the bank address of mask/flash ROM. When
bank base a 0000H to 3FFFH is used as a bank, ROBA8-0
is outputted to BA8-0. ROBA9-7 is used to generate the CS signal of
mask/flash ROM.

12-2-8. PS RAM Bank Control

This is a register to set the bank address of PS RAM. When bank
base a 4000H to 7FFFH is used as a bank. RABA8-0 is
outputted to BA8-0. ROBA8-6 is used to generate the CS signal of
PS RAM.

12-3. I/O Control

12-3-1. Special System Register

The special system register has a input port reading setup data defin-
ing the system configuration of hardware and software, offset register
setting a base address to relocatably place each internal register of
the PSC2 on the I/O space, COM decode control register, and shut-
down register.

This special system register uses fixed I/O address ranging from
07F0H to 07F1H. This address is in the area used by the FDC,
however this address is non-selected address of super I/O. So sys-
tems using the PSC2 are limited to a system in which address 07F0H
to 07F1H is not selected as an address decoded by the FDC, or a
system which uses the super I/O chip.

12-3-2. Interrupt Expansion and Assign Control

The interrupt control lines on the ISA bus used in the PSC2 are 6
lines: IRQ3, IRQ4, IRQ9, IRQ10, IRQ11, and IRQ15.

Each interrupt control line is outputted by taking OR between signals
on the ISA bus and the interrupt signal in the PSC2. UART2 can be
assigned to IRQ2, and UART1 can be assigned to IRQ4. PC-X dedi-
cated interrupt (IRQX) can be assigned to IRQ9. UART1, 2, and 5
can be assigned to IRQ10 and 11. UART1/2 and IRQX can be as-
signed to IRQ15.

IRQX is a signal generated by taking OR among interrupt control from
the POS dedicated device.

Assignment to each IRQ is controlled according to the setting of
interrupt assign register 0 and 1 (IAR0 and 1).

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